Driving circuit and driving method

Japanese Patent Application No. 2001-168520, filed on Jun. 4, 2001, is hereby incorporated by reference in its entirety.

The present invention relates to a driving circuit and a driving method.

Conventionally, as a liquid crystal panel (electro-optical device) which is used for an electronic equipment such as a portable telephone, there have been known a single matrix type liquid crystal panel and an active matrix type liquid crystal panel which uses switching elements such as thin film transistors (abbreviated as TFT hereinafter).

Although the single matrix type is advantageous compared to the active matrix type with respect to a point that the lowering of power consumption can be easily obtained, the single matrix type has a disadvantage that the multi-colorization and the moving picture display are difficult. With respect to a technique for lowering the power consumption in the single matrix type, there has been known a conventional technique disclosed in Japanese Patent Application Laid-open No. 7-98577, for example.

On the other hand, although the active matrix type has an advantage that this type is suitable for the multi-colorization and the moving picture display, the active matrix type has a disadvantage that the lowering of the power consumption is difficult.

Recently, in the field of the portable type electronic equipment such as a portable telephone set, the demand for multi-colorization and moving picture display has been increasing to provide images of high quality. Accordingly, in place of the single matrix type liquid crystal panel which has been used heretofore, the active matrix type liquid crystal panel is now popularly used.

However, with respect to the active matrix type liquid crystal panel used in the portable type electronic equipment, to cope with the demand for the alternating current driving of the liquid crystal and the lowering of voltage of power sources, a voltage level of counter electrodes (common electrodes) which face pixel electrodes in an opposed manner is inverted every scanning period, for example. Accordingly, due to the large charging/discharging of a liquid crystal panel and an operation current of an operational amplifier circuit which drives an analogue voltage, there has been a drawback that the realization of the lowering of power consumption is less than optimal.

One aspect of the present invention is directed to a driving circuit which drives an electro-optical device having scan lines, data lines and pixel electrodes which are specified by the scan lines and the data lines, the driving circuit performs:

a scan line-inversion-driving in which a voltage level of a counter electrode in a scanning period is set to a voltage level different from a voltage level in a preceding scanning period, the counter electrode facing a pixel electrode with an electro-optical material interposed therebetween; a driving in an Mth scanning period in which the voltage level of the counter electrode is set to one of first and second voltage levels; a driving in a virtual scanning period coming next to the Mth scanning period, in which the voltage level of the counter electrode is set to one of the first and second voltage levels different from the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period; and a driving in a first scanning period coming next to the virtual scanning period, in which the voltage level of the counter electrode is set to the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period.

Another aspect of the present invention is directed to a A driving method of driving an electro-optical device having scan lines, data lines and pixel electrodes which are specified by the scan lines and the data lines, comprising:

performing a scan line-inversion-driving in which a voltage level of a counter electrode is set in a scanning period to a voltage level different from a voltage level in a preceding scanning period, the counter electrode facing a pixel electrode with an electro-optical material interposed therebetween; performing a driving in an Mth scanning period in which the voltage level of the counter electrode is set to one of first and second voltage levels; providing a virtual scanning period next to the Mth scanning period, and performing a driving in the virtual scanning period, in which the voltage level of the counter electrode is set to one of the first and second voltage levels different from the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period; and performing a driving in a first scanning period coming next to the virtual scanning period, in which the voltage level of the counter electrode is set to the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period.

FIG. 1 is a block diagram showing an example of the configuration of a liquid crystal device;

FIG. 2 is a block diagram showing an example of the configuration of a data line driving circuit;

FIG. 3 is a block diagram showing an example of the configuration of a scan line driving circuit;

FIG. 4 is an illustrative describing various types of inversion driving methods in the liquid crystal device;

FIG. 5 is a timing waveform chart showing the change of voltage levels of a counter electrode and data line;

FIG. 6 is a diagram showing an example of the configuration of an operational amplifier circuit of AB class;

FIGS. 7A and 7B are diagrams describing a method of switching the operational amplifier when VCOM is switched;

FIG. 8 is a diagram showing an example of the configuration of a P-type operational amplifier;

FIG. 9 is a diagram showing an example of the configuration of an N-type operational amplifier;

FIG. 10 is a diagram describing a method of setting an output of the operational amplifier circuit in high impedance state at the time of switching the VCOM;

FIGS. 11A and 11B are also diagrams describing a method of setting an output of the operational amplifier circuit in high impedance state at the time of switching the VCOM;

FIGS. 12A and 12B are diagrams describing a storage capacitance method and an additional capacitance method;

FIG. 13 is a timing waveform chart showing the change of voltage levels of the counter electrode, data line, and scan line;

FIG. 14 is a diagram describing parasitic capacitance between the counter electrode and the data line;

FIG. 15 is a diagram describing parasitic capacitance between the counter electrode and the data line;

FIG. 16 is a diagram describing the change of the voltage level of the data line due to the parasitic capacitance;

FIG. 17 is a timing waveform chart describing a driving method of this embodiment;

FIG. 18 is a diagram describing an example of a detailed configuration of the operational amplifier circuit;

FIGS. 19A and 19B are timing waveform charts describing a method of performing an ON/OFF control of a current source of the operational amplifier circuit;

FIG. 20 is a timing waveform chart describing a method of performing an ON/OFF control of a driving transistor;

FIGS. 21A , 21 B and 21 C are diagrams describing a method of providing a clamp circuit to an output of the operational amplifier circuit;

FIGS. 22A , 22 B and 22 C are diagrams describing a method of lowering the power consumption by providing the clamp circuit;

FIG. 23 is a diagram describing the scan line inversion driving;

FIG. 24 is a timing waveform chart describing problems when an virtual scanning period is not provided; and

FIG. 25 is a timing waveform chart describing a method of providing a virtual scanning period.

Embodiments of the present invention are described hereinafter.

Note that the embodiments described hereunder do not in any way limit the scope of the invention defined by the claims laid out herein. Note also that all of the elements of these embodiments should not be taken as essential requirements to the means of the present invention.

The embodiments have been made in view of the above-mentioned technical problems, and according to the embodiments of the present invention, there are provided a driving circuit and a driving method which can realize the lowering of power consumption of an electro-optical device using a simple circuit configuration.

One embodiment of the present invention is directed to a driving circuit which drives an electro-optical device having scan lines, data lines and pixel electrodes which are specified by the scan lines and the data lines, the driving circuit performs:

a scan line-inversion-driving in which a voltage level of a counter electrode in a scanning period is set to a voltage level different from a voltage level in a preceding scanning period, the counter electrode facing a pixel electrode with an electro-optical material interposed therebetween; a driving in an Mth scanning period in which the voltage level of the counter electrode is set to one of first and second voltage levels; a driving in a virtual scanning period coming next to the Mth scanning period, in which the voltage level of the counter electrode is set to one of the first and second voltage levels different from the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period; and a driving in a first scanning period coming next to the virtual scanning period, in which the voltage level of the counter electrode is set to the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period.

According to this configuration, the electro-optical device can be driven by the scan line inversion driving. For example, the driving is performed in a state that the voltage level of the counter electrode is set to the first voltage level (or the second voltage level) in the first scanning period, the driving is performed in a state that the voltage level of the counter electrode is set to the second voltage level (or the first voltage level) in the second scanning period, and the driving is performed in a state that the voltage level of the counter electrode is set to the first voltage level (or the second voltage level) in the third scanning period. Further, the voltage level of the counter electrode is polarity-inverted in every frame, for example.

Further, in the driving circuit, the virtual scanning period is provided next to the Mth scanning period. Here, when the voltage level of the counter electrode becomes the second voltage level in the Mth scanning period and the subsequent first scanning period, for example, the voltage level of the counter electrode in the virtual period is set to the first voltage level. On the other hand, when the voltage level of the counter electrode becomes the first voltage level in the Mth scanning period and the subsequent first scanning period, the voltage level of the counter electrode in the virtual period is set to the second voltage level.

In this manner, it is possible to eliminate a situation that the voltage level of the counter electrode is not polarity-inverted between the adjacent scanning periods. Accordingly, the driving method which effectively utilizes the polarity inversion of the voltage level of the counter electrode can be realized.

Further, the driving circuit may comprise:

an operational amplifier circuit which drives a data line of the electro-optical device, wherein the operational amplifier circuit includes:

a first operational amplifier which drives the data line in a first period in which the voltage level of the counter electrode becomes the first voltage level; and a second operational amplifier which drives the data line in a second period in which the voltage level of the counter electrode becomes the second voltage level.

In this manner, the data line can be driven by the optimum operational amplifier corresponding to the change (polarity inversion) of the voltage level of the counter electrode so that the lowering of the power consumption can be realized.

Further, in the driving circuit, the operational amplifier circuit may include a selection circuit which selects an output of the first operational amplifier and connects the output to the data line in the first period in which the voltage level of the counter electrode becomes the first voltage level, and selects an output of the second operational amplifier and connects the output to the data line in the second period in which the voltage level of the counter electrode becomes the second voltage level.

Due to such a constitution, the changeover of the operational amplifiers in response to the transition of the voltage level of the counter electrode can be realized with the simple circuit configuration.

Further, in the driving circuit, the output of the selection circuit may be set to a high impedance state in a given period including a transition between the first and second periods.

Due to such a constitution, it is possible to change the voltage level of the data line to a given voltage level before driving the data line, by effectively utilizing the parasitic capacitance between the counter electrode and the data line, for example.

Further, in the driving circuit, the first operational amplifier may include:

a differential section; and an output section which has a first driving transistor of a first conductivity-type having a gate electrode which is controlled based on an output of the differential section, and the second operational amplifier may include:

a differential section; and an output section which has a second driving transistor of a second conductivity-type having a gate electrode which is controlled based on an output of the differential section.

Due to such a constitution, the data line can be driven by the first driving transistor of the first conductivity-type in the first period and can be driven by the second driving transistor of the second conductivity-type in the second period. Accordingly, it is possible to drive the data line with the proper driving transistor so that the lowering of power consumption of the driving circuit can be realized.

Further, the driving circuit may comprise:

an operational amplifier circuit which drives a data line of the electro-optical device, wherein, when the voltage level of the counter electrode changes from a second voltage level of a first power source side to a first voltage level of a second power source side, and a voltage level of the data line changes to the second power source side due to capacitive coupling caused by parasitic capacitance between the counter electrode and the data line, the operational amplifier circuit changes the voltage level of the data line, which has changed to the second power source side, to the first power source side and sets the voltage level of the data line to a voltage level corresponding to a gray scale level, and wherein, when the voltage level of the counter electrode changes from the first voltage level of the second power source side to the second voltage level of the first power source side and the voltage level of the data line changes to the first power source side due to the capacitive coupling caused by the parasitic capacitance between the counter electrode and the data line, the operational amplifier circuit changes the voltage level of the data line, which has changed to the first power source side, to the second power source side and sets the voltage level of the data line to a voltage level corresponding to a gray scale level.

Due to such a constitution, it is possible to change the voltage level of the data line in a given direction before driving the data line, by effectively utilizing the parasitic capacitance between the counter electrode and the data line. Then, the voltage level is changed by the operational amplifier circuit in the direction opposite to the changing direction so as to set the data line to the voltage level corresponding to the gray scale level. Accordingly, it is possible to determine the changing direction of the voltage level at the time of driving the data line to one direction so that the lowering of the power consumption of the operational amplifier circuit can be realized.

Further, in the driving circuit, the data line may be set to a high impedance state in a given period including a transition between a first period in which the voltage level of the counter electrode becomes the first voltage level and a second period in which the voltage level of the counter electrode becomes the second voltage level.

According to this embodiment, in the given period including a transition (a transition timing) between the first and second periods in which the voltage level of the counter electrode becomes the first and second voltage levels respectively, the data line is set to the high impedance state (non-driving state). Due to such a constitution, by effectively utilizing the parasitic capacitance between the counter electrode and the data line, for example, it is possible to change the voltage level of the data line to a desired voltage level before driving the data line, and it is also possible to return the charge, which is flown out from the data line due to the change of the voltage level of the counter electrode, to the power source side.

Another embodiment of the present invention is directed to a driving method of driving an electro-optical device having scan lines, data lines and pixel electrodes which are specified by the scan lines and the data lines, comprising:

performing a scan line-inversion-driving in which a voltage level of a counter electrode is set in a scanning period to a voltage level different from a voltage level in a preceding scanning period, the counter electrode facing a pixel electrode with an electro-optical material interposed therebetween; performing a driving in an Mth scanning period in which the voltage level of the counter electrode is set to one of first and second voltage levels; providing a virtual scanning period next to the Mth scanning period, and performing a driving in the virtual scanning period, in which the voltage level of the counter electrode is set to one of the first and second voltage levels different from the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period; and performing a driving in a first scanning period coming next to the virtual scanning period, in which the voltage level of the counter electrode is set to the voltage level to which the voltage level of the counter electrode has been set in the Mth scanning period.

Further, in the driving circuit, a data line may be driven by a first operational amplifier in a first period in which the voltage level of the counter electrode becomes the first voltage level, and

the data line may be driven by a second operational amplifier in a second period in which the voltage level of the counter electrode becomes the second voltage level.

Further, in the driving circuit, the data line may be set to a high impedance state in a given period including a transition between a first period in which the voltage level of the counter electrode becomes the first voltage level and a second period in which the voltage level of the counter electrode becomes the second voltage level.

Hereinafter, the embodiments of the present invention are explained in further detail in conjunction with attached drawings.

1. Liquid Crystal Device

FIG. 1 is a block diagram showing an example of a liquid crystal device to which an operational amplifier circuit of this embodiment is applied.

The liquid crystal device 10 (display device in a broad sense) includes a display panel 12 (LCD (Liquid Crystal Display) panel in a narrow sense), a data line driving circuit 20 (a source driver in a narrow sense), a scan line driving circuit 30 (gate driver in a narrow sense) a controller 40 and a power source circuit 42 . Here, the liquid crystal device 10 is not always required to include all of these circuit blocks and some circuit blocks may be omitted.

Here, the display panel 12 (electro-optical device in a broad sense) includes a plurality of scan lines (gate lines in a narrow sense), a plurality of data lines (source lines in a narrow sense) and pixel electrodes which are specified by the scan lines and the data lines. Here, TFTs (switching elements in a broad sense) are connected to the data lines and the pixel electrodes are connected to the TFTs thus constituting an active matrix type liquid crystal device.

To be more specific, the display panel 12 is formed as an active matrix substrate (glass substrate, for example). On this active matrix substrate, a plurality of scan lines G 1 to G M (M is a natural number of 2 or more) which are arranged in parallel in the Y direction in FIG. 1 and are respectively extended in the X direction in FIG. 1 and a plurality of data lines S 1 to S N (N is a natural number of 2 or more) which are arranged in parallel in the X direction in FIG. 1 and are respectively extended in the Y direction in FIG. 1 are arranged. Further, at a position corresponding to a crossing point of the scan line G K (1≦K≦M, K is a natural number) and the data line S L (1≦L≦N, L is a natural number), a TFT KL (switching element in a broad sense) is provided.

A gate electrode of the TFT KL is connected to the scan line G K , a source electrode of the TFT KL is connected to the data line S L , and a drain electrode of the TFT KL is connected to the pixel electrode PE KL . Between pixel electrode PE KL and a counter electrode VCOM (common electrode) which faces the pixel electrode PE KL with a liquid crystal element (electro-optical material in a broad sense) interposed therebetween, liquid crystal capacitance CL KL (liquid crystal element) and auxiliary capacitance CS KL are generated Further, liquid crystal is filled between the active matrix substrate on which the TFT KL , pixel electrodes PE KL and the like are formed and a counter substrate on which the counter electrode VCOM is formed. The transmittance of the liquid crystal element is changed in response to a voltage applied between the pixel electrodes PE KL and the counter electrode VCOM.

Here, the voltage levels (first and second voltage levels) applied to the counter electrode VCOM are generated by the power source circuit 42 . Further, without forming the counter electrode VCOM in a matted manner on the counter substrate, it is possible to form counter electrodes in a strip shape such that they correspond to respective scan lines.

The data line driving circuit 20 drives the data lines S 1 to S N of the display panel 12 based on the image data. On the other hand, the scan line driving circuit 30 sequentially performs the scanning driving of the scan lines G 1 to G M of the display panel 12 .

The controller 40 controls the data line driving circuit 20 , the scan line driving circuit 30 and the power source circuit 42 in accordance with a content set by a host computer such as a central processing unit (hereinafter referred to as “CPU”) not shown in the drawing. To be more specific, the controller 40 performs the setting of operational modes and supplies vertical synchronous signals and horizontal synchronous signals which are generated in the inside of the controller 40 to the data line driving circuit 20 and the scan line driving circuit 30 , while the controller 40 performs the control of polarity inversion timing of voltage level of the counter electrode VCOM to the power source circuit 42 .

The power source circuit 42 generates various types of voltage levels (gray scale voltages) and the voltage level of the counter electrode VCOM necessary for driving the display panel 12 based on reference voltages supplied from the outside.

In the liquid crystal device 10 having such a constitution, under the control of the controller 40 , based on the image data supplied from the outside, the data line driving circuit 20 , the scan line driving circuit 30 and the power source circuit 42 drive the display panel 12 in a cooperative manner.

Here, in FIG. 1 , although the liquid crystal device 10 is configured to incorporate the controller 40 therein, the controller 40 may be provided outside the liquid crystal device 10 . Alternately, a host computer may be incorporated into the liquid crystal device 10 together with the controller 40 . Further, a portion of or all of the data line driving circuit 20 , the scan line driving circuit 30 , the controller 40 and the power source circuit 42 may be formed on the display panel 12 .

1.1 Data Line Driving Circuit

FIG. 2 shows an example of the constitution of the data line driving circuit 20 shown in FIG. 1 .

The data line driving circuit 20 includes a shift register 22 , line latches 24 , 26 , a DAC 28 (digital/analogue conversion circuit, data voltage generation circuit in a broad sense), and an output buffer 29 (operational amplifier circuits).

The shift register 22 includes a plurality of flip-flops which are provided corresponding to respective data lines and are sequentially connected with each other. The shift register 22 holds enable input/output signals in synchronism with clock signals CLK and sequentially shifts the enable input/output signals EIO to neighboring flip-flops in synchronism with the clock signals CLK.

The image data (DIO) is inputted to the line latch 24 per a unit of 18 bits (6 bits (gray scale data)×3 (respective colors R, G, B)) from the controller 40 , for example. The line latch 24 latches the image data (DIO) in synchronism with the enable input/output signals EIO which are sequentially shifted by respective flip-flops of the shift register 22 .

The line latch 26 latches the image data for 1 horizontal scanning unit which is latched by the line latch 24 in synchronism with horizontal synchronous signals LP supplied from the controller 40 .

The DAC 28 generates analogue data voltages to be supplied to respective data lines. To be more specific, the DAC 28 , based on digital image data from the line latch 26 , selects any one of gray scale voltages from the power source circuit 42 shown in FIG. 1 and outputs the analogue data voltages corresponding to the digital image data.

The output buffer 29 outputs the data voltages from the DAC 28 to the data lines after buffering them and drives the data lines. To be more specific, the output buffer 29 includes operational amplifier circuits OPC in voltage follower connection provided for respective data lines and these operational amplifier circuits OPC output the data voltages from the DAC 28 to respective data lines after performing the impedance conversion.

Here, in FIG. 2 , the data line driving circuit is configured such that the digital image data is subjected to the digital/analogue conversion and the analogue data is outputted to the data lines through the output buffer 29 . However, the analogue video signals may be subjected to a sample holding and may be outputted to the data lines through the output buffer 29 .

1.2 Scan Line Driving Circuit

FIG. 3 shows an example of the constitution of the scan line driving circuit 30 shown in FIG. 1 .

The scan line driving circuit 30 includes a shift register 32 , a level shifter 34 and an output buffer 36 .

The shift register 32 includes a plurality of flip-flops which are provided corresponding to respective scan lines and are sequentially connected to each other, The shift register 32 , when enable input/output signals EIO are held by the flip-flops in synchronism with clock signals CLK, sequentially shifts the enable input/output signals EIO to neighboring flip-flops in synchronism with the clock signals CLK. Here, the inputted enable input/output signals EIO are vertical synchronous signals which are supplied from the controller 40 .

The level shifter 34 shifts the voltage levels outputted from the shift register 32 to the voltage levels corresponding to the capacities of the liquid crystal element of the display panel 12 and the TFTs. The high voltage level of 20V to 50V, for example, is necessary as the voltage level and hence, the high dielectric strength process different from that of the other logic circuit parts is used.

The output buffer 36 outputs the scanning voltage which is shifted by the level shifter 34 after buffering the scanning voltage and drives the scan lines.

2. Operational Amplifier Circuit

2.1 Line Inversion Driving

The liquid crystal element has a property that when the direct current voltage is applied to the liquid crystal element for a long time, the liquid crystal element is deteriorated. To prevent such deterioration, a driving method which inverts the polarity of the voltage applied to the liquid crystal element every given period become necessary. As such a driving method, there have been known a frame inversion driving, a scanning (gate) line inversion driving, a data (source) line inversion driving method, a dot inversion driving and the like.

Among these driving methods, although the frame inversion driving method exhibits the lowering of power consumption, the method has a disadvantage that the image quality is not so good. Further, although the data line inversion driving and the dot inversion driving exhibit the good image quality, these methods have a disadvantage that the high voltage is necessary for driving the display panel.

Accordingly, this embodiment adopts the scan line inversion driving shown in FIG. 4 . In this scan line inversion driving, the voltage applied to the liquid crystal element has the polarity thereof inverted every scanning period (every scan line). For example, the voltage of positive polarity is applied to the liquid crystal element in the first scanning period (scan line), the voltage of negative polarity is applied to the liquid crystal element in the second scanning period, and the voltage of positive polarity is applied to the liquid crystal element in the third scanning period. On the other hand, in the next frame, the voltage of negative polarity is applied to the liquid crystal element in the first scanning period, the voltage of positive polarity is applied to the liquid crystal element in the second scanning period, and the voltage of negative polarity is applied to the liquid crystal element in the third scanning period.

Then, in this scan line inversion driving, the voltage level of the counter electrode VCOM has the polarity thereof inverted every scanning period.

To be more specific, as shown in FIG. 5 , the voltage level of the counter electrode VCOM becomes VC 1 (first voltage level) in the period T 1 of positive polarity (first period) and becomes VC 2 (second voltage level) in the period T 2 of negative polarity(second period).

Here, the period T 1 of positive polarity is a period in which the voltage level of the data line S (pixel electrode) becomes higher than the voltage level of the counter electrode VCOM. In this period T 1 , the voltage of positive polarity is applied to the liquid crystal element. On the other hand, the period T 2 of negative polarity is a period in which the voltage level of the data line S (pixel electrode) becomes lower than the voltage level of the counter electrode VCOM. In this period T 2 , the voltage of negative polarity is applied to the liquid crystal element. Further, VC 2 is the voltage level which is obtained by performing the inversion of polarity of VC 1 with respect to a given voltage level.

In this manner, by performing the inversion of polarity of the counter electrode VCOM, the voltage necessary for driving the display panel can be lowered. Accordingly, the dielectric strength of the driving circuit can be lowered leading to the simplifying of the manufacturing process and the reduction of the manufacturing cost.

However, it has been found that the method which performs the inversion of polarity of the counter electrode VCOM has following drawbacks in view of the lowering of power consumption of circuits.

For example, as indicated by A 1 , A 2 in FIG. 5 , when the period is changed from the period T 1 to the period T 2 , there may be a case (A 1 ) that the voltage level of the data line S is changed to the low potential side and also there exists a case (A 2 ) that the voltage level of the data line S is changed to the high potential side. In the same manner, as indicated by A 3 , A 4 in FIG. 5 , when the period is changed from the period T 2 to the period T 1 , there may be a case (A 3 ) that the voltage level of the data line S is changed to the high potential side and also there exists a case (A 4 ) that the voltage level of the data line S is changed to the low potential side.

For example, when the gray scale of the data line S in the period T 1 is 63 and the gray scale of the data line S in the period T 2 is also 63, the voltage level of the data line S is changed to the low potential side as indicated by A 1 in FIG. 5 . On the other hand, when the gray scale of the data line S in the period T 1 is 0 and the gray scale of the data line S in the period T 2 is also 0, the voltage level of the data line S is changed to the high potential side.

In this manner, to perform the inversion of polarity of the counter electrode VCOM in the active matrix type liquid crystal device, the direction of the change of the voltage level of the data line S depends on the gray scale level. Accordingly, there has been a drawback that the power consumption lowering technique of the single matrix type liquid crystal device disclosed in Japanese Patent Application Laid-open No. 7-98577 cannot be applied directly or as it is.

Therefore, in the conventional active matrix type liquid crystal device, as an operational amplifier circuit (OPC including the output buffer 29 shown in FIG. 2 ) for driving the data line, an AB class (push-pull method) operational amplifier circuit shown in FIG. 6 has been used.

This AB class operational amplifier circuit includes a differential section 300 and an output section 310 which has a P-type (first conductivity-type in a broad sense) driving transistor PT 53 and an N-type (second conductivity-type in a broad sense) driving transistor NT 55 .

Here, the differential section 300 includes P-type transistors PT 51 , PT 52 which have gate electrodes thereof connected to an output DQ of the differential section 300 in common, N-type transistors NT 51 , NT 52 which have gate electrodes thereof connected to inputs I, XI of the differential section 300 , and a current source IS 51 .

The output section 310 includes an inversion circuit which is constituted of an N-type transistor NT 53 which has a gate electrode thereof connected to an output XDQ (inversion output) of the differential section 300 and a current source IS 52 . Further, the output section 310 includes the P-type driving transistor PT 53 which has a gate electrode thereof connected to the output XDQ of the differential section 300 , the N-type driving transistor NT 55 which has a gate electrode thereof connected to an output BQ of the inversion circuit, an N-type transistor NT 54 which has a gate electrode thereof connected to a VSS, and capacitance CC for phase compensation.

In the operational amplifier circuit shown in FIG. 6 , an output Q of the output section 310 is connected to the input XI (inversion input) of the differential section 300 thus establishing a voltage follower connection.

Further, the current sources IS 51 , IS 52 are constituted of N-type transistors which have gate electrodes thereof connected to the reference voltage (constant voltage), for example.

In the AB class operational amplifier circuit shown in FIG. 6 , the output section 310 includes both of the P-type driving transistor PT 53 and the N type driving transistor NT 55 . Accordingly, when the voltage levels are changed over as indicated by A 1 , A 4 in FIG. 5 , the N-type driving transistor NT 55 is operated so that the voltage level of the data line S can be rapidly lowered to the low potential side. On the other hand, when the voltage levels are changed over as indicated by A 2 , A 3 in FIG. 5 , the P-type driving transistor PT 53 is operated so that the voltage level of the data line S can be rapidly elevated to the high potential side. Accordingly, in the liquid crystal device which performs the scan line inversion driving while inverting the polarity of the counter electrode VCOM, in most cases, the AB class operational amplifier circuit shown in FIG. 6 has been used as an operational amplifier circuit which an output buffer of a data line driving circuit includes.

However, the AB class operational amplifier circuit shown in FIG. 6 includes three paths in which an electric current flows, that is, the paths for electric currents I 51 , I 52 , I 53 and hence, the electric current which is consumed uselessly is increased thus giving rise to a drawback that the power consumption is increased. Particularly, with respect to this type of AB class operational amplifier circuit, to properly control gate electrodes of the driving transistors PT 53 , NT 55 , a circuit having a constitution which uses four or more current paths is used in many cases. When such a circuit constitution is adopted, the power consumption is further increased. On the other hand, when the electric currents I 51 , I 52 , I 53 are reduced in amount to lower the power consumption, this brings about the lowering of response speed and the deterioration of frequency characteristics.

Further, with respect to the operational amplifier circuit shown in FIG. 6 , a large number of these operational amplifier circuits are provided corresponding to respective data lines as shown in FIG. 2 . Accordingly, when the power consumption of each operational amplifier circuit is increased, the power consumption of the liquid crystal device is increased corresponding to the number of the operational amplifier circuits thus giving rise to a drawback that the lowering of power consumption of the liquid crystal device is considerably hindered.

Accordingly, to solve such a drawback, this embodiment adopts a method which will be explained hereinafter.

2.2 Changeover of Operational Amplifiers

First of all, in this embodiment, the operational amplifiers for driving the data line are changed over corresponding to the changeover of the voltage level of the counter electrode VCOM.

To be more specific, as shown in FIG. 7A , in the period T 1 (first period, period of positive polarity shown in FIG. 5 ) in which the voltage level of the counter electrode VCOM becomes VC 1 (first voltage level), the data line is driven using the operational amplifier OP 1 . On the other hand, in the period T 2 (second period, period of negative polarity shown in FIG. 5 ) in which the voltage level of the counter electrode VCOM becomes VC 2 (second voltage level which is obtained by inverting the polarity of VC 1 ), the data line is driven using the operational amplifier OP 2 which is different from the operational amplifier OP 1 .

An example of the constitution of the operational amplifier circuit which can realize such a driving method is shown in FIG. 7 B. The operational amplifier circuit includes the operational amplifier OP 1 (P-type first operational amplifier), the operational amplifier OP 2 (N-type second operational amplifier) and a selection circuit 70 .

Here, the operational amplifier OP 1 (P-type) includes, as shown in FIG. 7B , a differential section 50 and an output section 52 which has a P-type driving transistor PT 13 and a current source IS 12 , for example. Here, the P-type driving transistor PT 13 has a gate electrode thereof controlled based on an output (inversion output) of the differential section 50 .

Further, the operational amplifier OP 2 (N-type) includes, as shown in FIG. 7B , a differential section 60 and an output section 62 which has an N-type driving transistor NT 23 and a current source IS 22 , for example. Here, the N-type driving transistor NT 23 has a gate electrode thereof controlled based on an output (inversion output) of the differential section 60 .

Here, the current sources IS 12 , IS 22 are served for supplying constant currents and each current source can be constituted of an N-type transistor which connects a gate electrode thereof to a reference voltage, a depression-type transistor or a resistance element. Further, in FIG. 7B , the operational amplifier circuit may be constituted without using the current sources IS 12 , IS 22 .

The selection circuit 70 , when the counter electrode VCOM become VC 1 (in the period T 1 ), selects the output Q 1 of the operational amplifier OP 1 and connects the output Q 1 with the data line S. On the other hand, the selection circuit 70 , when the counter electrode VCOM become VC 2 (in the period T 2 ), selects the output Q 2 of the operational amplifier OP 2 and connects the output Q 2 with the data line S. Due to such an operation, the data line S can be driven by the operational amplifier OP 1 in the period T 1 and can be driven by the operational amplifier OP 2 in the period T 2 .

FIG. 8 shows an example of the constitution of the operational amplifier OP 1 . This operational amplifier OP 1 is a P-type operational amplifier whose output section 52 includes a P-type driving transistor PT 13 while eliminating an N-type driving transistor.

A differential section 50 of the operational amplifier OP 1 includes P-type transistors PT 11 , PT 12 which have gate electrodes thereof connected in common to an output DQ 1 of the differential section 50 , N-type transistors NT 11 , NT 12 which have gate electrodes thereof connected to inputs I 1 , XI 1 of the differential section 50 and a current source IS 11 which is provided at the VSS (second power source) side.

The output section 52 of the operational amplifier OP 1 includes the P-type transistor PT 13 which has a gate electrode thereof connected to an output XDQ 1 (inversion output) of the differential section 50 , a current source IS 12 which is provided at the VSS side and capacitance CC 1 for phase compensation.

The operational amplifier OP 1 shown in FIG. 8 has an output Q 1 thereof connected to an input XI 1 (inversion input) of the differential section 50 thus establishing a voltage follower connection.

FIG. 9 shows an example of the constitution of the operational amplifier OP 2 . This operational amplifier OP 2 is an N-type operational amplifier whose output section 62 includes an N-type driving transistor NT 23 while eliminating a P-type driving transistor.

A differential section 60 of the operational amplifier OP 2 includes a current source IS 21 which is provided at the VDD (first power source) side, P-type transistors PT 21 , PT 22 which have gate electrodes thereof connected to inputs I 2 , XI 2 of the differential section 60 , and N-type transistors NT 21 , NT 22 which have gate electrodes thereof connected in common to an output DQ 2 of the differential section 60 .

The output section 62 of the operational amplifier OP 2 includes a current source IS 22 which is provided at the VDD side, the N-type transistor NT 23 which has a gate electrode thereof connected to an output XDQ 2 (inversion output) of the differential section 60 , and capacitance CC 2 for phase compensation.

The operational amplifier OP 2 shown in FIG. 9 has an output Q 2 thereof connected to an input XI 2 (inversion input) of the differential section 60 thus establishing a voltage follower connection.

In the operational amplifier OP 1 shown in FIG. 8 , the paths in which the electric current flows are constituted of only two paths I 11 , I 12 . In the same manner, in the operational amplifier OP 2 shown in FIG. 9 , paths in which the electric current flows are constituted of only two paths I 21 , I 22 . Accordingly, compared to the AB class operational amplifier circuit shown in FIG. 6 which uses three or more electric current paths, these operational amplifiers OP 1 , OP 2 can reduce the current which flows uselessly so that the lowering of power consumption can be achieved.

Further, with respect to the AB class operational amplifier circuit shown in FIG. 6 , when the current supply ability of the driving transistors PT 53 , NT 55 is decreased, the data-line driving ability is lowered. Accordingly, it is not possible to effectively reduce the current I 53 which flows the paths of the driving transistors PT 53 , NT 55 .

To the contrary, with respect to the operational amplifier OP 1 shown in FIG. 8 , in a situation (B 15 shown in FIG. 17 which will be explained later) where it is not so much necessary to lower the voltage level of the output Q 1 to the low potential side, the current I 12 which flows in the current source IS 12 can be made extremely small. In the same manner, with respect to the operational amplifier OP 2 shown in FIG. 9 , in a situation (BS shown in FIG. 17 which will be explained later) where it is not so much necessary to elevate the voltage level of the output Q 2 to the high potential side, the current I 22 which flows in the current source IS 22 can be made extremely small. Accordingly, compared to the AB class operational amplifier circuit shown in FIG. 6 which cannot make the current I 53 at the output section 310 sufficiently small, the operational amplifiers OP 1 , OP 2 shown in FIGS. 8 and 9 can make the currents I 12 , I 22 which flow in the output sections 52 , 62 sufficiently small so that the power consumption can be extremely reduced.

Then, in this embodiment, as shown in FIG. 7A , only the operational amplifier OP 1 whose power consumption is extremely small is used in the period T 1 and only the operational amplifier OP 2 whose power consumption is also extremely small is used in the period T 2 . Accordingly, compared to a conventional method using the AB class operational amplifier circuit shown in FIG. 6 which consumes a large amount of power in the whole periods (T 1 and T 2 ), the power consumption of the liquid crystal device can be drastically reduced.

Further, with respect to the operational amplifier circuit of this embodiment shown in FIG. 7B , the operational amplifier circuits are provided corresponding to respective data lines as shown in FIG. 2 and hence are provided corresponding to the number of data lines whereby the number of operational amplifier circuits is extremely large. Accordingly, when the power consumption of each operational amplifier circuit can be decreased, the power consumption of the liquid crystal device can be reduced corresponding to the number of operational amplifier circuits so that the power consumption of the liquid crystal device can be drastically reduced.

2.3 Setting of Output of Operational Amplifier Circuit to High Impedance State

Further, in this embodiment, the output of the operational amplifier circuit can be set to the high impedance state.

To be more specific, as shown in FIG. 10 , this embodiment adopts a driving method in which in a given period (including transition timing) at the time of a transition of the period from the period T 1 (first period) in which the voltage level of the counter electrode VCOM becomes VC 1 (first voltage level) to the period T 2 (second period) in which the voltage level of the counter electrode VCOM becomes VC 2 (second voltage level), the output of the operational amplifier circuit is set to the high impedance state (HIZ).

An example of the constitution of an operational amplifier circuit which can realize such a driving method is shown in FIG. 11 A. This operational amplifier circuit includes an operational amplifier OP 1 (P-type), an operational amplifier OP 2 (N-type) and a selection circuit 70 . Here, an output of the selection circuit 70 is set to the high impedance state in the given period at the time of changing over the period between the period T 1 and the period T 2 .

To be more specific, the selection circuit 70 includes transfer gates TG 1 , TG 2 (path transistors, switching elements in a broad sense) where a P-type transistor and an N-type transistor are connected in parallel. The transfer gate TG 1 is subjected to an ON/OFF control in response to a signal SEL 1 and the transfer gate TG 2 is subjected to an ON/OFF control in response to a signal SEL 2 .

FIG. 11B shows timing waveforms of the ON/OFF control of the transfer gates TG 1 , TG 2 using the signals SEL 1 , SEL 2 .

As shown in FIG. 11B , when the signal SEL 1 becomes active (H level) in the period T 1 in which the voltage level of the counter electrode VCOM becomes VC 1 , the transfer gate TG 1 is turned on (conductive state). Then, the operational amplifier OP 1 is selected and the output Q 1 of the operational amplifier OP 1 is connected to the data line S. Accordingly, the data line S is driven by the P-type operational amplifier OP 1 .

On the other hand, when the signal SEL 2 becomes active in the period T 2 in which the voltage level of the counter electrode VCOM becomes VC 2 , the transfer gate TG 2 is turned on. Then, the operational amplifier OP 2 is selected and the output Q 2 of the operational amplifier OP 2 is connected to the data line S. Accordingly, the data line S is driven by the N-type operational amplifier OP 2 .

Then, when both of the signals SEL 1 , SEL 2 become non-active (L level), both of the transfer gates TC 1 , TG 2 are turned off (non-conductive state). Then, the data line S is driven by neither the operational amplifier OP 1 nor the operational amplifier OP 2 , and the data line S become the high impedance state (HIZ). Due to such operations, it is possible to set the data line S to the high impedance state at the time of a transition of period between the periods T 1 and T 2 .

In this manner, according to this embodiment, using the signals SEL 1 , SEL 2 which become active in the periods T 1 and T 2 and make the periods in which these signals become active not overlapped to each other, the ON/OFF control of the transfer gates TG 1 , TG 2 (switching elements) is performed. Due to such a control, the changeover driving of the data line S using the operational amplifiers OP 1 , OP 2 and the setting of the data line S to the high impedance can be realized with the simple circuit constitution and the simple circuit control.

Although the high impedance control of the outputs of the operational amplifiers are realized by using the method which sets the output of the selection circuit 70 to the high impedance state in FIGS. 11A and 11B , the high impedance control may be realized by a method which sets the outputs Q 1 , Q 2 of the operational amplifiers OP 1 , OP 2 to the high impedance state.

3. Principle of Lowering of Power Consumption

Subsequently, the principle of the method of lowering the power consumption according to this embodiment is explained.

In the liquid crystal device, to enhance the image quality while holding the voltage level of the pixel electrode in the non-selective periods, the auxiliary capacitance is connected to the pixel electrode for assisting the liquid crystal capacitance. As a method of forming such auxiliary capacitance, there exist a storage capacitance method shown in FIG. 12 A and an addition capacitance method shown in FIG. 12 B.

In the storage capacitance method shown in FIG. 12A , the auxiliary capacitance CS is formed between the pixel electrode and the counter electrode VCOM. This can be realized by separately forming wiring of the counter electrode VCOM on the active matrix substrate, for example. On the other hand, in the addition capacitance method shown in FIG. 12B , the auxiliary capacitance CS is formed between the pixel electrode and the scan line (gate line) of the preceding stage. This can be realized by a layout which overlaps the pattern of the pixel electrode with the pattern of the scan line of the preceding stage.

Although the power consumption lowering method of this embodiment is applicable to both the storage capacitance method shown in FIG. 12 A and the addition capacitance method shown in FIG. 12B , to simplify the explanation, a case in which the power consumption lowering method is applied to the storage capacitance method shown in FIG. 12A is explained by way of an example.

Here, in the storage capacitance method shown in FIG. 12A , the parasitic capacitance between the gate and the drain of the TFT and the parasitic capacitance between the gate and the source of the TFT act in the direction to suppress the change of the voltage level of the data line. To the contrary, in the addition capacitance method shown in FIG. 12B , the voltage level of the scan line of the preceding stage is also changed at the time of changing of the voltage level of the counter electrode VCOM. Accordingly, the change of the voltage level of the scan line acts in the direction to assist the change of the voltage level of the data line. Accordingly, with respect to the method of the embodiment which changes the voltage level of the data line in response to the change of the voltage level of the counter electrode VCOM and lowers the power consumption by utilizing the change of the voltage level of the data line, the addition capacitance method shown in FIG. 12B is more effective.

FIG. 13 conceptually shows an example of signal waveforms of the data line S, the counter electrode VCOM and the scanning signal line G in the case of the storage capacitance method.

As shown in FIG. 13 , the voltage levels of the data line S and the counter electrode VCOM are subjected to the inversion of polarity with reference to a given voltage level every scanning period. Then, when the voltage level of the data line S has a potential higher than that of the counter electrode VCOM, the voltage applied to the liquid crystal element becomes the positive polarity, while when the voltage level of the counter electrode VCOM has a potential higher than that of the data line S, the voltage applied to the liquid crystal element becomes the negative polarity. In this manner, by inverting the polarity of the voltage applied to the liquid crystal element every scanning period, it is possible to prevent the direct voltage from being applied to the liquid crystal element for a long time so that the life of the liquid crystal element can be prolonged.

Here, when the counter electrode VCOM is subjected to the inversion of polarity so that the voltage level is changed from VC 1 to VC 2 or from VC 2 to VC 1 as shown in FIG. 13 , the change of the voltage level of the counter electrode VCOM is transmitted to the data line S due to the capacitive coupling caused by the parasitic capacitance between the counter electrode VCOM and the data line S.

Here, as shown in FIG. 14 , the parasitic capacitance CPA PIX between the counter electrode VCOM and the data line S per 1 pixel can be expressed by a following equation.

CPA PIX ={1 /CDS+ 1/( CL+CS )} −1   (1)

In this equation (1), CDS is the parasitic capacitance between the drain and the source of the TFT, CL is the liquid crystal capacitance and CS is the auxiliary capacitance. In the equation (1), the parasitic capacitance between the gate and the drain of the TFT and the parasitic capacitance between the gate and the source of the TFT are ignored.

Then, as shown in FIG. 15 , the parasitic capacitance CPA between the counter electrode VCOM and the data line S per 1 data line can be expressed by a following equation.

CPA=CPA PIX ×( M− 1)  (2)

In the equation (2), M indicates the number of scan lines. The reason that CPA is not calculated as CPA PIX ×M but is calculated as CPA PIX ×(M−1) is that there is no influence of the parasitic capacitance CPA PIX with respect to the pixel selected by the scan line.

For example, in the above-mentioned equations (1) and (2), assuming that CL+CS=0.1 pico farad (pf), CDS=0.05 pf and the number of scan lines M=228, the parasitic capacitance per 1 pixel CPA PIX becomes approximately 0.33 pf and the parasitic capacitance per 1 data line CPA becomes approximately 7.6 pf.

In this manner, the parasitic capacitance of a level which cannot be ignored is formed between the counter electrode VCOM and the data line. Accordingly, as shown in FIG. 16 , when the voltage level of the counter electrode VCOM is changed with the data line S held in the non-driven state, the voltage level of the data line S is also changed due to the capacitive coupling caused by the parasitic capacitance CPA.

For example, as shown in FIG. 16 , when the voltage level of the counter electrode VCOM is changed from VC 1 to VC 2 or from VC 2 to VC 1 , the voltage level of the data line S is changed from VS 1 to VS 2 or from VS 2 to VS 1 . Here, in an ideal case that other parasitic capacitance is not formed on the data line S, the relationship VS 2 −VS 1 =VC 2 −VC 1 is established among the voltage levels. However, in an actual operation, since the parasitic capacitance is present between the data line S and the substrate as well as between the data line S and the atmosphere, the relationship among the voltage levels becomes VS 2 −VS 1 <VC 2 −VC 1 .

In this embodiment, the lowering of power consumption of the liquid crystal device is realized by positively utilizing such a change of the voltage level of the data line S caused by the parasitic capacitance CPA.

For example, at B 1 in a timing waveform chart shown in FIG. 17 , the voltage level of the counter electrode VCOM is changed from VC 1 at the VSS (second power source) side to VC 2 at the VDD (first power source) side. In this case, according to this embodiment, at the timing of changeover of the voltage level, the data line S (output of the operational amplifier circuit) is set to the high impedance state as indicated by B 2 (see FIG. 10 to FIG. 11 B).

By setting the data line S to the high impedance state in this manner, the data line S becomes the non-driven state. Accordingly, due to the parasitic capacitance CPA between the counter electrode VCOM and the data line S (see FIG. 14 to FIG. 16 ), the voltage level of the data line S is changed to the VDD side (high potential side) as indicated by B 3 in FIG. 17 .

Then, in this embodiment, as indicated by B 4 in FIG. 17 , in the period T 2 in which the voltage level of the counter electrode VCOM becomes VC 2 , the data line S is driven by the N-type operational amplifier OP 2 (see FIG. 7A to FIG. 9 ). Accordingly, the voltage level of the data line which has changed to the VDD side as indicated by B 3 in FIG. 17 is changed to the VSS side (low potential side) by driving the operational amplifier OP 2 as indicated by B 5 and is set to the voltage level as indicated by B 6 corresponding to the gray scale level (see FIG. 5 ).

In this case, OP 2 is the N-type operational amplifier having the N-type driving transistor NT 23 as shown in FIG. 9 . Accordingly, by utilizing the driving ability of the driving transistor NT 23 provided at the VSS side, the voltage level of the data line S can be easily changed to the VSS side (low potential side) as indicated by B 5 shown in FIG. 17 . In other words, since it is unnecessary to change the voltage level of the data line S to the VDD side (high potential side), the electric current which flows in the current source IS 22 in FIG. 9 can be reduced (or eliminated). Accordingly, the power consumption of the operational amplifier circuit can be lowered so that the power consumption of the liquid crystal device can be lowered.

On the other hand, at B 11 in FIG. 17 , the voltage level of the counter electrode VCOM is changed from VC 2 of the VDD side to VC 1 of the VSS side. In this case, according to this embodiment, the data line S is set to the high impedance state as indicated by B 12 at the timing of transition of the voltage level.

When the data line s is set to the high impedance state, the data line S becomes the non-driven state. Accordingly, as indicated by B 13 in FIG. 17 , the voltage level of the data line S is changed to the VSS side due to the parasitic capacitance CPA generated between the counter electrode VCOM and the data line S.

Then, in this embodiment, as indicated by B 14 shown in FIG. 17 , in the period T 1 in which the voltage level of the counter electrode VCOM becomes VC 1 , the data line S is driven by the P-type operational amplifier OP 1 . Accordingly, the voltage level of the data line S which has changed to the VSS side as indicated by B 13 shown in FIG. 17 is changed to the VDD side by driving the operational amplifier OP 1 as indicated by B 15 and is set to the voltage level as indicated by B 16 corresponding to the gray scale level.

In this case, OP 1 is the P-type operational amplifier having the P-type driving transistor PT 13 as shown in FIG. 8 . Accordingly, by utilizing the driving ability of the driving transistor PT 13 provided at the VDD side, the voltage level of the data line S can be easily changed to the VDD side as indicated by B 15 shown in FIG. 17 . In other words, since it is unnecessary to change the voltage level of the data line S to the VSS side, the electric current which flows in the current source IS 12 in FIG. 8 can be reduced (or eliminated). Accordingly, the power consumption of the operational amplifier circuit can be lowered so that the power consumption of the liquid crystal device can be lowered.

For example, according to a method which does not set the data line S to the high impedance state at the time of changing over the voltage level of the counter electrode VCOM, the data line S always becomes the driving state due to the operational amplifier circuit. Accordingly, even when the voltage level of the counter electrode VCOM is changed, the capacitive coupling caused by the parasitic capacitance CPA does not bring about the changes of the voltage level of the data line S as indicated by B 3 and B 13 in FIG. 17 . Accordingly, as has been explained previously in conjunction with A 1 to A 4 in FIG. 5 , the direction that the voltage level of the data line S is changed depends on the gray scale level and it is difficult to specify the changing direction to one direction. Accordingly, there is no way but to use the AB class operational amplifier circuit shown in FIG. 6 which can change the voltage level of the data line S to the VDD side as well as to the VSS side with the same driving force. However, since the AB class operational amplifier circuit exhibits the large power consumption, it has been difficult for the liquid crystal device to realize the lowering of power consumption.

To the contrary, by positively utilizing the parasitic capacitance CPA between the counter electrode VCOM and the data line S, this embodiment has succeeded in changing the voltage level of the data line S to the VDD side as well as to the VSS side before driving the data line S as indicated by B 3 and B 13 in FIG. 17 .

Here, when the voltage level of the data line S is changed to the VDD side before driving the data line S as indicated by B 3 in FIG. 17 , the direction that the voltage level of the data line S is changed thereafter is not dependent on the gray scale level and is set to the VSS side. Accordingly, as the operational amplifier which drives the data line S, it is possible to use the N-type operational amplifier OP 2 which exhibits the weak driving force at the VDD side but the strong driving force at the VSS side.

On the other hand, when the voltage level of the data line S is changed to the VSS side before driving the data line S as indicated by B 13 in FIG. 17 , the direction that the voltage level of the data line S is changed thereafter is not dependent on the gray scale level and is set to the VDD side. Accordingly, as the operational amplifier which drives the data line S, it is possible to use the P-type operational amplifier OP 1 which exhibits the weak driving force at the VSS side but the strong driving force at the VDD side.

Here, both of P-type and N-type operational amplifiers OP 1 , OP 2 exhibit the small power consumption. In this manner, this embodiment can drastically lower the power consumption compared to the method which uses the AB class operational amplifier circuit shown in FIG. 6 .

The change width of the voltage level of the data line S at B 3 , B 13 in FIG. 17 is small when parasitic capacitance (parasitic capacitance between the data line S and the atmosphere, for example) other than the parasitic capacitance CPA is large. Then, when the change width of the voltage level of the data line S is small, depending on the gray scale level, there may arise a state in which the voltage level of the data line S is to be inversely changed to the VDD side at B 5 or to the VSS side at B 15 in FIG. 17 .

However, even when such a state arises, the change of the voltage level at B 3 assists the driving of the N-type operational amplifier OP 2 . That is, the time which the current source IS 22 (see FIG. 9 ) of the operational amplifier OP 2 needs to change the voltage level of the data line S to the VDD side can be shortened. In the same manner, the change of the voltage level at B 13 also assists the driving of the P-type operational amplifier OP 1 . That is, the time which the current source IS 12 (see FIG. 8 ) of the operational amplifier OP 1 needs to change the voltage level of the data line S to the VSS side can be shortened.

Although the voltage level of the data line S is changed as indicated by B 3 , B 13 in FIG. 17 by setting the output of the operational amplifier circuit to the high impedance state, the voltage level of the data line S may be changed at the time of changeover of the counter electrode VCOM by other method which uses an additional transistor (pre-charge transistor, for example) for changing the voltage level, for example.

However, according to the method which sets the output of the operational amplifier circuit to the high impedance state shown in FIG. 17 , it is possible to change the voltage level of the data line S as indicated by B 3 , B 13 by effectively utilizing the charging/discharging of the display panel which is generated by the counter electrode VCOM. Accordingly, the method can enhance the lowering of power consumption compared to the above-mentioned method using the additional transistor.

4. Detailed Example of Operational Amplifier Circuit

FIG. 18 shows an example of a detailed constitution of the operational amplifier circuit.

The operational amplifier circuit shown in FIG. 18 differs from the operational amplifier circuit which has been explained in conjunction with FIG. 7A to FIG. 11B with respect to a point that the operational amplifier OP 1 includes the N-type transistors NT 14 , NT 16 and the P-type transistor PT 14 , while the operational amplifier OP 2 includes the P-type transistors PT 24 , PT 26 and the N-type transistor PT 24 .

In FIG. 18 , the N-type transistors NT 13 , NT 15 having the reference voltage (bias voltage) VB 1 connected to gate electrodes thereof and the P-type transistors PT 23 , PT 25 having the reference voltage (bias voltage) VB 2 connected to gate electrodes thereof respectively correspond to the current sources IS 11 , IS 12 , IS 21 , IS 22 in FIGS. 8 and 9 . Further, RP indicates a resistance for protecting an output of the operational amplifier circuit from static electricity.

4.1 ON/OFF Control of Current Sources

In this embodiment, using the transistors NT 14 , NT 16 , PT 24 , PT 26 shown in FIG. 18 , the ON/OFF control of the current sources IS 11 (NT 13 ), IS 12 (NT 15 ), IS 21 (PT 23 ), IS 22 (PT 25 ) of the operational amplifiers OP 1 , OP 2 is performed so as to realize the ON/OFF control of the operations of the operational amplifiers.

Here, signals OFF 1 D, OFF 1 Q are connected to the gate electrodes of the N-type transistors NT 14 , NT 16 , while signals XOFF 2 D, XOFF 2 Q are connected to the gate electrodes of the P-type transistors PT 24 , PT 26 . Then, these signals OFF 1 D, OFF 1 Q, XOFF 2 D, XOFF 2 Q are subjected to a signal control as shown in a timing waveform chart in FIG. 19A , for example. Here, ‘X’ of the signals XOFF 2 D, XOFF 2 Q means “negative logic”.

For example, in the period T 1 (first period) in which the counter electrode VCOM becomes VC 1 , the signals OFF 1 D, OFF 1 Q become H level (active) and the N-type transistors NT 14 , NT 16 in FIG. 18 are turned on. Accordingly, the current flows into the current sources IS 11 (NT 13 ), IS 12 (NT 15 ) of the operational amplifier OP 1 so that the operational amplifier OP 1 becomes the operable state.

Further, in this period T 1 , the signals XOFF 2 D, XOFF 2 Q become H level (non-active) and the P-type transistors PT 24 , PT 26 are turned off. Accordingly, the current which flows into the current sources IS 21 (PT 23 ), IS 22 (PT 25 ) of the operational amplifier OP 2 is cut off so that the operational amplifier OP 2 becomes the inoperable state.

In this manner, in the period T 1 , while the operational amplifier OP 1 is set to the operable state, the operational amplifier OP 2 is set to the inoperable state and hence, the power consumption can be lowered. That is, compared to a case in which both of the operational amplifiers OP 1 , OP 2 are set to the operable state, the power consumption can be halved. Then, in the period T 1 , only the output of the operational amplifier OP 1 is selected by the selection circuit 70 and the data line S is driven only by the operational amplifier OP 1 . Accordingly, even when the operational amplifier OP 2 becomes the inoperable state in the period T 1 , there arises no problem with respect to the driving of the data line S.

In the period T 2 (second period) in which the counter electrode VCOM becomes VC 2 , the signals OFF 1 D, OFF 1 Q become L level (non-active) and the N-type transistors NT 14 , NT 16 in FIG. 18 are cut off. Accordingly, the current flows into the current sources IS 11 , IS 12 of the operational amplifier OP 1 so that the operational amplifier OP 1 becomes the inoperable state.

Further, in this period T 2 , the signals XOFF 2 D, XOFF 2 Q become L level (active) and the P-type transistors PT 24 , PT 26 are turned on. Accordingly, the current flows into the current sources IS 21 , IS 22 of the operational amplifier OP 2 so that the operational amplifier OP 2 becomes the operable state.

In this manner, in the period T 2 , while the operational amplifier OP 2 is set to the operable state, the operational amplifier OP 1 is set to the inoperable state and hence, the power consumption can be lowered. That is, compared to a case in which both of the operational amplifiers OP 1 , OP 2 are set to the operable state, the power consumption can be halved. Then, in the period T 2 , only the output of the operational amplifier OP 2 is selected by the selection circuit 70 and the data line S is driven only by the operational amplifier OP 2 . Accordingly, even when the operational amplifier OP 1 becomes the inoperable state in the period T 2 , there arises no problem with respect to the driving of the data line S.

In this manner, according to this embodiment, with the provision of the transistors NT 14 , NT 16 , PT 24 , PT 26 which are controlled in response to the signals OFF 1 D, OFF 1 Q, XOFF 2 D, XOFF 2 Q, the current sources of the operational amplifier which is not used can be turned off thus succeeding in the lowering of the power consumption of the operational amplifier circuit.

Here, the signals OFF 1 D, OFF 1 Q, XOFF 2 D, XOFF 2 Q may be subjected to a signal control shown in a timing waveform chart in FIG. 19 B.

That is, in FIG. 19B , although the signals OFF 1 D, XOFF 2 D are changed in response to the transition of the periods T 1 , T 2 , the signals OFF 1 Q, XOFF 2 Q are not changed in response to the transition of the periods T 1 , T 2 . Here, while the signal OFF 1 Q is fixed to the H level, the signal XOFF 2 Q is fixed to the L level

Then, by changing the signals OFF 1 D, XOFF 2 D, the current sources IS 11 , IS 22 which the differential sections of the operational amplifiers OP 1 , OP 2 in FIG. 18 include are subjected to the ON/OFF control.

On the other hand, by fixing the signals OFF 1 Q, XOFF 2 Q to the H level and L level, the current sources IS 12 , IS 22 which the output sections of the operational amplifiers OP 1 , OP 2 include always become the ON state.

For example, when the electric current which flows in the current sources IS 11 , TS 21 of the differential section of the operational amplifier is large, the response speed and the frequency characteristics of the operational amplifier can be enhanced so that the current is large in general. Accordingly, by performing the ON/OFF control of the current which flows in the current sources IS 11 , IS 21 , the more effective lowering of power consumption can be realized.

On the other hand, as has been explained in conjunction with B 5 , B 15 in FIG. 17 , in this embodiment, the current supply ability (driving ability) is not required so much with respect to the current sources IS 12 , IS 22 of the output section of the operational amplifier. Accordingly, even when the current which flows in the current sources IS 12 , IS 22 is not subjected to the ON/OFF control but is always allowed to flow into the current sources IS 12 , IS 22 , the transistors PT 13 , NT 23 are turned off through the transistors PT 14 , NT 24 in response to the signals SEL 1 , SEL 2 and hence, the power consumption is not increased so much. Then, by allowing the electric current to always flow in the current sources IS 12 , IS 22 , the voltage levels of the outputs Q 1 , Q 2 of the operational amplifiers OP 1 , OP 2 can be made stable and the voltage levels of the outputs Q 1 , Q 2 can be set to L level (VSS) and H level (VDD) when the driving transistors PT 13 , NT 23 are in the OFF state. Accordingly, as will be explained later, a drawback which may arise due to a phenomenon that the voltage level of the outputs Q 1 , Q 2 becomes unstable can be effectively prevented.

Although the control is performed so as to cut off the electric current which flows in the current sources IS 11 , IS 12 , IS 21 , IS 22 in FIGS. 19A and 19B , the control may be performed so as to restrict or decrease the electric current without completely cutting off the current.

4.2 ON/OFF Control of Driving Transistors

In this embodiment, the ON/OFF control of the driving transistors PT 13 , NT 23 of the operational amplifiers OP 1 , OP 2 is performed using the transistors PT 14 , NT 24 shown in FIG. 18 thus preventing the outputs Q 1 , Q 2 of the operational amplifiers OP 1 , OP 2 from becoming unstable.

Here, the signal SEL 1 is connected to the gate electrode of the P-type transistor PT 14 . This signal SEL 1 is a signal which is also used for the ON/OFF control of the transfer gate TG 1 and instructs the selection/non-selection of the operational amplifier OP 1 (see FIGS. 11 A- 11 B).

Further, an inversion signal of the signal SEL 2 is connected to the gate electrode of the N-type transistor NT 24 . This signal SEL 2 is a signal which is also used for the ON/OFF control of the transfer gate TG 2 and instructs the selection/non-selection of the operational amplifier OP 2 .

These signals SEL 1 , SEL 2 are subjected to a signal control as shown in a timing waveform chart in FIG. 20 , for example.

For example, in the period T 1 in which the counter electrode VCOM becomes VC 1 , the signal SEL 1 becomes H level (active) and the transfer gate TG 1 in FIG. 18 is turned on. Accordingly, the operational amplifier OP 1 is selected and the output Q 1 is connected to the data line S.

On the other hand, in the period T 1 , the signal SEL 2 becomes L level (non-active) and the N-type transistor NT 24 to which the inversion signal of the signal SEL 2 is inputted is turned on. Accordingly, the signal XDQ 2 which is connected to the gate electrode of the driving transistor NT 23 becomes L level so that the driving transistor NT 23 is turned off. Accordingly, the voltage level of the output Q 2 of the operational amplifier OP 2 is pulled toward the VDD side due to the current source IS 22 and is set to H level. That is, in the period T 1 in which the operational amplifier OP 2 becomes the inoperable state, it is possible to prevent the voltage level of the output Q 2 of the operational amplifier OP 2 from becoming unstable.

Further, in the period T 2 in which the counter electrode VCOM becomes VC 2 , the signal SEL 2 becomes H level (active) and the transfer gate TG 2 in FIG. 18 is turned on. Accordingly, the operational amplifier OP 2 is selected and the output Q 2 is connected to the data line S.

On the other hand, in the period T 2 , the signal SEL 1 becomes L level (non-active) and the P-type transistor PT 14 to which the signal SEL 1 is inputted is turned on. Accordingly, the signal XDQ 1 which is connected to the gate electrode of the driving transistor PT 13 becomes H level so that the driving transistor PT 13 is turned off. Accordingly, the voltage level of the output Q 1 of the operational amplifier OP 1 is pulled toward the VSS side due to the current source IS 12 and is set to L level. That is, in the period T 2 in which the operational amplifier OP 1 becomes the inoperable state, it is possible to prevent the voltage level of the output Q 1 of the operational amplifier OP 1 from becoming unstable.

As explained above, according to this embodiment, in the period before the operational amplifier OP 2 is selected and the operational amplifier OP 2 drives the data line S, as indicated by E 1 in FIG. 20 , the gate electrode of the driving transistor NT 23 which the operational amplifier OP 2 includes becomes L level so that the driving transistor NT 23 is turned off. Since the current source IS 22 is always in the ON state at this point of time, the voltage level of the output Q 2 of the operational amplifier OP 2 is changed to the VDD side and becomes H level.

Accordingly, even when the transfer gate TG 2 is turned on based on the selection of the operational amplifier OP 2 as indicated by E 2 in FIG. 20 thereafter, the adverse influence which may be caused by the redistribution of charge can be minimized.

That is, in this embodiment, before driving the data line S using the operational amplifier OP 2 , the data line S (output of the operational amplifier circuit) is set to the high impedance state as indicated by E 3 in FIG. 20 . Then, by changing the counter electrode VCOM from VC 1 to VC 2 in this high impedance state, the voltage level of the data line S is elevated as explained in conjunction with B 3 in FIG. 17 .

However, assuming a case in which the output Q 2 of the operational amplifier OP 2 becomes L level when the transfer gate TG 2 shown in FIG. 18 is turned on, the voltage level of the data line S which is once elevated as indicated by B 3 in FIG. 17 is lowered due to the redistribution of charge. This gives rise to a phenomenon in which the subsequent driving of the data line by the operational amplifier OP 2 is hindered.

According to this embodiment, in the period before the data line S is driven by the operational amplifier OP 2 , the driving transistor NT 23 of the operational amplifier OP 2 is turned off as indicated by E 1 in FIG. 20 and the output Q 2 of the operational amplifier OP 2 becomes H level and hence, the adverse influence caused by the redistribution of charge can be minimized thus preventing the above-mentioned phenomenon.

In the same manner, according to this embodiment, in the period before the operational amplifier OP 1 is selected and the operational amplifier OP 1 drives the data line S, as indicated by E 11 in FIG. 20 , the gate electrode of the driving transistor PT 13 which the operational amplifier OP 1 includes becomes H level so that the driving transistor PT 13 is turned off. Since the current source IS 12 is always in the ON state at this point of time, the voltage level of the output Q 1 of the operational amplifier OP 1 is changed to the VSS side and becomes L level.

Accordingly, even when the transfer gate TG 1 is turned on in response to the selection of the operational amplifier OP 1 as indicated by E 12 in FIG. 20 thereafter, the adverse influence which may be caused by the redistribution of charge can be minimized.

That is, in this embodiment, before driving the data line S using the operational amplifier OP 1 , the data line S is set to the high impedance state as indicated by E 13 in FIG. 20 . Then, by changing the voltage level of the counter electrode VCOM from VC 2 to VC 1 in this high impedance state, the voltage level of the data line S is lowered as explained in conjunction with B 13 in FIG. 17 .

However, assuming a case in which the output Q 1 of the operational amplifier OP 1 becomes H level when the transfer gate TG 1 shown in FIG. 18 is turned on, the voltage level of the data line S which is once lowered as indicated by B 13 in FIG. 17 is elevated due to the redistribution of charge. This gives rise to a phenomenon in which the subsequent driving of the data line by the operational amplifier OP 1 is hindered.

According to this embodiment, in the period before the data line S is driven by the operational amplifier OP 1 , the driving transistor PT 13 of the operational amplifier OP 1 is turned off as indicated by E 11 in FIG. 20 and the output Q 1 of the operational amplifier OP 1 becomes L level and hence, the adverse influence caused by the redistribution of charge can be minimized thus preventing the above-mentioned phenomenon.

5. Clamp Circuit

Here, to further lower the power consumption of the liquid crystal device, as shown in FIG. 21A , this embodiment performs a high impedance control of the output Q of the operational amplifier circuit and provides a clamp circuit 80 to the output Q. With the provision of this clamp circuit 80 , the output Q (data line S) of the operational amplifier circuit is clamped in a voltage range equal to or wider than a voltage range between the power sources VDD, VSS of the operational amplifier circuit. Accordingly, it is possible to return the excessive charge to the power source VDD side or the power source VSS side so that the power consumption of the liquid crystal device can be lowered.

As shown in FIG. 21A , the clamp circuit 80 includes a diode DI 1 (clamp element) which is inserted between the power source VSS (second power source) and the data line S and a diode DI 2 which is inserted between the data line S and the power source VDD (first power source). Here, the diode DI 1 is a diode which sets the direction advancing from the power source VSS to the data line s as the forward direction and the diode DI 2 is a diode which sets the direction advancing from the data line S to the power source VDD as the forward direction.

FIG. 21B shows an example of the element structure of the diode DI 1 provided on the VSS side. As shown in FIG. 21B , the diode DI 1 uses a p well region p − which is connected to the power source VSS through an active region p + as a positive-polarity-side electrode and an active region n + as a negative-polarity-side electrode.

FIG. 21C shows an example of the element structure of the diode DI 2 provided on the VDD side. As shown in FIG. 21C , the diode D 12 uses an active region p + as a positive-polarity-side electrode and an n well region n − which is connected to the power source VDD through an active region n + as a negative-polarity-side electrode.

These diodes DI 1 , D 12 can be also used as protective circuits for the operational amplifier circuit. To be more specific, these diodes DI 1 , DI 2 may be incorporated into an I/O circuit (I/O pad) of a semiconductor device in which the operational amplifier circuit (driving circuit) is formed.

Here, without providing the diodes to both of the VDD side and the VSS side, the diode may be provided on only one side. Further, the output transistors (transfer gates TG 1 , TG 2 in FIG. 18 , for example) of the operational amplifier circuit may be used as the diodes DI 1 , DI 2 (clamp circuit).

Subsequently, the principle of the method of lowering the power consumption with the provision of the clamp circuit 80 shown in FIG. 21A is explained. Here, to simplify the explanation, the explanation is made hereinafter assuming that the power sources VSS, VDD are set to 0V, 5V and VC 1 , VC 2 of the counter electrode VCOM are also set to 0V, 5V.

For example, assume that the written voltage VS (gray scale voltage) of the data line S is 3V when the counter electrode VCOM is 0V as indicated by F 1 in FIG. 22 A. Further, assume that the counter electrode VCOM is changed from 0V (VC 1 ) to 5V (VC 2 ) as indicated by F 1 , F 2 in FIG. 22A in this state. At this point of time, in this embodiment, since the output of the operational amplifier circuit is set to the high impedance state (see FIG. 10 to FIG. 11 B), due to the parasitic capacitance CPA generated between the counter electrode VCOM and the data line S (see FIG. 16 ), the data line S is going to be changed from 3V (VS) to VS+VC 2 =8V.

However, in this embodiment, the clamp circuit 80 is provided to the output of the operational amplifier circuit as shown in FIG. 21 A. Accordingly, even when the data line S is going to be changed to 8V, the voltage of 8V is clamped by the clamp circuit 80 thus resulting in VDD+0.6V=5.6 V. Here, 0.6V is the forward direction voltage of PN junction of the diode.

Then, when the voltage of 8V is changed to 5.6V by clamping, the charge of EQ 1 =(8V−5.6V)×CPA is returned to the power source VDD side and is utilized again for performing the operation of the operational amplifier circuit included in the driving circuit. That is, the energy which is used for changing the counter electrode VCOM of the display panel is not wasted but is returned to the power source and is reused so that the power consumption can be lowered.

Further, even when the voltage level of the data line S (output Q of the operational amplifier circuit) is lowered from 8V to 5.6V, this voltage level is still sufficiently higher than the gray scale voltage (0 to 5V). Accordingly, this voltage level does not hinder the data line driving method of this embodiment which has been explained in conjunction with B 3 , B 5 , B 13 , B 15 in FIG. 17 .

Then, assume that the written voltage VS (gray scale voltage) of 2V is written in the data line S in the state that the counter electrode VCOM is 5V as indicated by F 3 in FIG. 22 A. Further, assume that the counter electrode VCOM is changed from 5V (VC 2 ) to 0V (VC 1 ) as indicated by F 3 , F 4 in FIG. 22 A. At this point of time, in this embodiment, since the output of the operational amplifier circuit is set to the high impedance state, due to the parasitic capacitance CPA between the counter electrode VCOM and the data line S, the data line S is going to be changed from 2V to −3V.

However, in this embodiment, the clamp circuit 80 is provided to the output of the operational amplifier circuit as shown in FIG. 21 A. Accordingly, even when the data line S is going to be changed to −3V, the voltage of −3V is clamped by the clamp circuit 80 thus resulting in VSS−0.6V=−0.6 V.

Then, when the voltage of −3V is changed to −0.6V by clamping, the charge of EQ 2 ={−6−(−3V)}×CPA is returned to the power source VSS side and is utilized again so that the power consumption can be lowered.

As explained above, in this embodiment, to change the voltage level of the data line S using the parasitic capacitance CPA, the output of the operational amplifier circuit is set to the high impedance state at the time of changeover of the counter electrode VCOM. Then, as shown in FIG. 22B , the output of the operational amplifier circuit is clamped to the voltage range (5.6V to −0.6V) which is equal to or wider than the voltage level (5V to 0V) between the power sources VDD, VSS of the operational amplifier circuit. Accordingly, the charges EQ 1 =2.4V×CPA, EQ 2 =2.4V×CPA which become excessive due to these clamping operations are returned to the power sources VDD, VSS so that the power consumption of the liquid crystal device can be lowered.

Here, to facilitate the return of the charge at the time of clamping, it is desirable that the power source for the operational amplifier circuit and the power source for the clamp circuit are provided as circuits different from each other.

To be more specific, as indicated by F 5 in FIG. 22C , when the power sources of the operational amplifier circuit are constituted of power sources VDD, VSS (first and second power sources) and the power sources of the clamp circuit are constituted of power sources VDD′, VSS′ (third and fourth power sources), the relationship VDD−VSS>VDD′−VSS′ is established. That is, the voltage range of the power sources VDD′, VSS′ of the clamp circuit is set narrower than the voltage range of the power sources VDD, VSS of the operational amplifier circuit. For example, when the voltage range of VDD, VSS is 5V to 0V, the voltage range of VDD′, VSS′ is set to 4.4V to 0.6V.

Due to such a constitution, as indicated by F 6 in FIG. 22C , it is possible to increase the charge which can be returned to the power source sides compared to FIG. 22 B. For example, while the charge of EQ 1 =EQ 2 =2.4V×CPA is returned to the power source side in FIG. 22B , the charge of EQ 1 =EQ 2 =3.0V×CPA is returned to the power source side in FIG. 22 C. Accordingly, the charge which is returned to the power source side can be increased so that the further lowering of the power consumption of the liquid crystal device can be realized.

The power sources VDD′, VSS′ of the clamp circuit can be generated by utilizing the voltage generation function (gray scale voltage generation function) of the power source circuit 42 in FIG. 1 .

Further, when the forward voltage of the diode is set to VBD, it is desirable that the relationship VDD′≧VDD−VBD, VSS′≦VSS+VBD is established. For example, when the voltage VDD is 5V and the voltage VSS is 0V, the relationship VDD′>4.4V, VSS′<0.6V is established.

Due to such a constitution, a phenomenon that the driving current of the operational amplifier circuit flows in the power sources VDD′ and VSS′ of the clamp circuit at the time of driving the data line using the operational amplifier circuit can be prevented. Accordingly, the proper data line driving of the operational amplifier circuit can be realized.

The power consumption lowering method which sets the output of the operational amplifier circuit to the high impedance state at the time of changeover of the voltage level of the counter electrode VCOM and provides the clamp circuit to the output of the operational amplifier circuit is also effectively applicable to the AB class operational amplifier circuit shown in FIG. 6 . That is, also with respect to the AB class operational amplifier circuit, the excessive charge can be returned to the power source side and the power consumption can be lowered by an amount corresponding to the excessive charge.

6. Virtual Scanning Period

In the scanning (gate) line inversion driving which has been explained in conjunction with FIG. 4 , as shown in FIG. 23 , the polarity of voltage applied to the liquid crystal element is inverted every scanning period (scan line) and is also inverted every frame. Accordingly, it is possible to prevent the phenomenon that the direct current voltage is applied to the liquid display element for a long time so that the deterioration of the liquid crystal element can be prevented.

In such a scan line inversion driving, when the number M of the scan lines is an even number (228 pieces, for example) as indicated by J 1 , J 2 , J 3 and J 4 in FIG. 23 , the polarity of the applied voltage in the final Mth scanning period becomes equal to the polarity of the applied voltage in the first scanning period of the next frame. For example, at J 1 and J 2 in FIG. 23 , both of these polarities become negative polarities and at J 3 and J 4 in FIG. 23 , both of these polarities become positive polarities.

Accordingly, when the display panel having the even number M of scan lines is driven by the driving method of this embodiment shown in FIG. 17 , it has been found that following drawbacks arise.

For example, in the (M−1)th scanning period (the period in which the (M−1)th scan line is selected) as shown in FIG. 24 , VCOM becomes VC 1 and VC 1 is lower than the gray scale voltage and hence, the (M−1)th scanning period becomes the period T 1 in which the voltage applied to the liquid crystal element has the positive polarity. Further, in the final Mth scanning period (the period in which the Mth scan line is selected), VCOM becomes VC 2 and VC 2 is higher than the gray scale voltage and hence, the Mth scanning period becomes the period T 2 in which the voltage applied to the liquid crystal element has the negative polarity. Further, in the first scanning period (the period in which the first scan line is selected) of the next frame, VCOM becomes VC 1 and hence, the first scanning period becomes the period T 2 in which the voltage applied to the liquid crystal element has the negative polarity.

That is, in FIG. 24 , both of the Mth scanning period and the first scanning period of the next frame are periods T 2 of negative polarity and hence, even when the scanning period is changed from the Mth scanning period to the first scanning period, VCOM are held at VC 2 as indicated by K 1 and the polarity is not inverted. Further, in the Mth scanning period as well as in the first scanning period, the data line is driven by the N-type operational amplifier OP 2 .

In this manner, since VCOM per se is not subjected to the inversion of polarity at K 1 in FIG. 24 , even when the output of the operational amplifier circuit becomes the high impedance state as indicated by K 2 , the voltage level of the data line S is not changed. That is, although the voltage level of the data line is changed to the VSS side as indicated by B 13 since VCOM is subjected to the inversion of polarity at B 11 in FIG. 17 , the voltage level of the data line is not changed with respect to K 1 in FIG. 24 .

Accordingly, in the subsequent first scanning period, the direction that the voltage level of the data line is changed depends on the gray scale level (see A 1 to A 4 in FIG. 5 ) and it is difficult to specify the direction to one direction. Accordingly, when the data line is driven by the N-type operational amplifier OP 2 as indicated by K 3 in FIG. 24 in the first scanning period, there arises a case in which it is necessary to spend a long time until the voltage level of the data line is set to the voltage level corresponding to the gray scale level. This is because that when the direction that the voltage level of the data line is changed is set to the VDD side, it is necessary to drive the data line using the current source IS 22 in FIG. 9 which exhibits the low current supply ability.

Accordingly, in this embodiment, a method which inserts a virtual (dummy) scanning period between the Mth scanning period and the first scanning period is adopted.

To be more specific, first of all, as a presumption, the display panel (electro-optical device) is driven by the scan line inversion driving (inversion driving which sets the voltage level of the counter electrode VCOM in the scanning period to the voltage level which is different from the voltage level of the preceding scanning period) shown in FIG. 23 .

Then, as indicated by L 1 in FIG. 25 , in the Mth (M being an even number) scanning period, the driving is performed while setting VCOM to VC 2 (either one voltage level of VC 1 , VC 2 in a broad sense).

Subsequently, as indicated by L 2 in FIG. 25 , the virtual (dummy) scanning period is provided next to the Mth scanning period. In this virtual scanning period, the driving is performed while setting VCOM to VC 1 (the other voltage level different from the above-mentioned one voltage level in a broad sense). That is, the counter electrode VCOM is subjected to the inversion of polarity.

Subsequently, as indicated by L 3 in FIG. 25 , in the first scanning period next to the virtual scanning period, the driving is performed while setting VCOM to VC 2 (the above-mentioned one voltage level in a broad sense).

Further, in response to such changeover of the voltage level of the counter electrode VCOM, as indicated by L 4 , L 5 , L 6 in FIG. 25 , the operational amplifier is changed over from the operational amplifier OP 1 (P type) to the operational amplifier OP 2 (N type), from the operational amplifier OP 2 to the operational amplifier OP 1 , and from the operational amplifier OP 1 (P type) to the operational amplifier OP 2 (N type) sequentially. That is, the driving is performed in the scanning period using the operational amplifier different from the operational amplifier used in the preceding scanning period.

Further, at the time of changing over the voltage level of the counter electrode VCOM, the output (data line) of the operational amplifier circuit is set to the high impedance state.

Due to such operations, although the counter electrode VCOM is not subjected to the inversion of polarity at K 1 in FIG. 24 , VCOM is always subjected to the inversion of polarity as indicated by L 1 , L 2 , L 3 in FIG. 25 . Accordingly, it is possible to change the voltage level of the data line before driving by positively utilizing the parasitic capacitance CPA as indicated by B 3 , B 13 in FIG. 17 . As a result, as indicated by B 5 , B 15 in FIG. 17 , it is possible to specify the changing direction of the voltage level to one direction without depending on the gray scale level and hence, the A class operational amplifiers OP 1 , OP 2 with small power consumption can be used. As a result, the lowering of the power consumption of the liquid crystal device can be enhanced.

In the virtual scanning period shown in FIG. 25 , the data line is driven using the operational amplifier corresponding to the polarity of the period. For example, the virtual scanning period is the period T 1 of positive polarity at L 2 in FIG. 25 and hence, the data line is driven using the P-type operational amplifier OP 1 which has the high ability to change the voltage level to the VDD side. On the other hand, when the virtual scanning period is the period T 2 of negative polarity, the data line is driven using the N-type operational amplifier OP 2 having the high ability to change the voltage level to the VSS side.

Further, in the virtual scanning period, the scan line driving circuit 30 shown in FIG. 1 does not drive the scan lines G 1 to GM but performs the virtual driving of virtual scan lines.

To be more specific, when the number M of the scan lines is 228, for example, the controller 40 shown in FIG. 1 inputs the enable input/output signal EIO shown in FIG. 3 to the shift resister 32 not every 228 scanning period but every 229 scanning period. Due to such an operation, in the virtual scanning period which comes next to the Mth scanning period, the enable input/output signal EIO is not present in the shift resister 32 so that the driving of the actual scan lines is not performed.

Here, the method which provides the virtual scanning periods as shown in FIG. 25 is also applicable to a driving method in which one frame is divided into a plurality of driving fields.

Further, the method shown in FIG. 25 is also applicable to a driving method in which an additional transistor (pre-charge transistor, for example) is provided to the output of the operational amplifier circuit and the voltage level of the data line is changed before driving.

Here, the present invention is not limited to this embodiment and various modifications are conceivable within the scope of the spirit of the present invention.

For example, although the embodiment has been explained in conjunction with the case in which the present invention is applied to the active matrix type liquid crystal device using the TFT, the liquid crystal device to which the present invention is applicable is not limited to such a liquid crystal device.

Further, the constitution of the operational amplifier circuit is not limited to the constitution which has been explained in this embodiment.

Further, the present invention is not limited to the liquid crystal device (LCD panel) and is also applicable to an electro-luminescence (EL) device, an organic EL device and a plasma display device.

Further, the present invention is not limited to the scan line inversion driving and is also applicable to other inversion driving methods.

Still further, with respect to the inventions according to dependent claims among the present inventions, a portion of constituent elements of dependent claims can be omitted. Further, an essential part of the invention of one independent claim of the present invention may be made dependent on other independent claim.