Power-on/off reset circuit

1. Field of the Invention

This invention relates to power-on/off reset circuits that reset semiconductor integrated circuits in power-on mode and power-off mode.

2. Description of the Related Art

FIG. 7A shows a typical example of a reset circuit that operates in a power-on mode. This reset circuit comprises a capacitor CL, a p-type field effect transistor (FET) MP 1 , and an inverter I 1 . Specifically, one end of the capacitor CL is grounded, while the other end (corresponding to a terminal POC) is connected with a positive source voltage V DD via the p-type FET MP 1 and is also connected with an input of the inverter I 1 . At time t 0 , the positive source voltage V DD starts increasing the level thereof as shown in FIG. 7B, so that the capacitor CL starts being charged. During the progression of the charging of the capacitor CL, the potential of the terminal POC gradually increases. Since the input voltage of the inverter I 1 connected with the terminal POC is normally below the prescribed threshold allowing inversion of the inverter I 1 , the output of the inverter I 1 (see ‘OUT’ shown in FIG. 7C) gradually increases in accordance with the increase of the source voltage V DD . At time t 1 when a certain time has elapsed after the source voltage V DD reaches the prescribed level, the potential of the terminal POC exceeds the threshold so as to allow an inversion of the inverter I 1 . Therefore, in the rise time of the source voltage V DD , the reset circuit of FIG. 7A provides at the output (OUT) thereof a reset signal having a high (H) level, which is designated by a symbol ‘R’ in FIG. 7 C. However, the aforementioned reset circuit has a drawback in that it cannot output a reset signal in a power-off mode. This will be described further with reference to FIGS. 10A to 10 C. In the reset circuit shown in FIG. 10A which is an equivalent of the reset circuit of FIG. 7A, the source voltage V DD gradually drops in a power-off mode as shown in FIG. 10B, while the potential of the terminal POC correspondingly drops with a certain delay time due to the time constant of the capacitor CL and the FET MP 1 . For this reason, the input voltage of the inverter I 1 connected with the terminal POC would not be reduced to be lower than the source voltage V DD , so that the output of the inverter I 1 remains at a low level (LO) as shown in FIG. 10 C. That is, the aforementioned reset circuit of FIG. 10A cannot reliably provide a reset signal in a power-off mode.

It is strongly demanded in semiconductor integrated circuits (ICs) and LSI devices that reset signals are reliably provided in a power-off mode, which will be described below.

Suppose that two integrated circuits IC 1 and IC 2 operate independently of each other by their respective power sources as shown in FIG. 8, wherein the integrated circuit IC 1 provides control signals to control the operation of the integrated circuit IC 2 . If the integrated circuit IC 1 does not provide a reset function in a power-off mode, it may provide ‘unexpected’ control signals to the integrated circuit IC 2 , which may cause problems unexpectedly. In the worst case, the integrated circuit IC 2 may run away and depart from the normal operation. Therefore, it is required that the integrated circuit IC 1 reliably provides a reset function in a power-off mode, which will ensure that the integrated circuit IC 2 will be normally set without problems.

Suppose that an integrated circuit (IC) has a function of ringing sound by a speaker as shown in FIG. 9 . If it does not provide a reset function in a power-off mode, the speaker may unexpectedly produce a high-pitch electronic sound like ‘peep’, which is offensive.

It is an object of the invention to provide a power on/off reset that is capable of reliably providing reset signals in both a power-on mode and a power-off mode.

A power-on/off reset circuit comprises a capacitor, a first transistor, a second transistor, a first current mirror circuit, a second current mirror circuit, and an inverter. In a power-on mode where the source voltage (V DD ) gradually increases in level, the capacitor is charged via the first transistor. The first current mirror circuit comprising a pair of transistors allows a current to flow therein in proportion to a potential of the capacitor. The second transistor converts the current to a voltage, which is input to the inverter to provide a first reset signal in the power-on mode. In a power-off mode where the source voltage gradually decreases in level, the second current mirror circuit comprising a pair of transistors temporarily increases the input voltage of the inverter to provide a second reset signal.

Thus, the power-on/off reset circuit is capable of reliably providing reset signals in both the power-on mode and power-off mode.

These and other objects, aspects, and embodiments of the present invention will be described in more detail with reference to the following drawing figures, in which:

FIG. 1 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a first embodiment of the invention;

FIG. 2A shows variations of a POC potential together with a source voltage V DD in a power-on mode;

FIG. 2B shows variations of input voltage ND 1 of an inverter I 2 in the power-on mode;

FIG. 2C shows an output of the inverter I 2 in the power-on mode;

FIG. 3A shows variations of a POC potential together with a source voltage V DD in a power-off mode;

FIG. 3B shows variations of input voltage ND 1 of the inverter I 2 in the power-off mode;

FIG. 3C shows an output of the inverter I 2 in the power-off mode;

FIG. 4 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a second embodiment of the invention;

FIG. 5A shows variations of a POC potential together with a source voltage V DD in its rise time;

FIG. 5B shows an output of an inverter I 1 in the rise time of the source voltage V DD ;

FIG. 5C shows an output of a NOR gate NR in the rise time of the source voltage V DD ;

FIG. 6 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a third embodiment of the invention;

FIG. 7A shows an example of a reset circuit that operates in a power-on mode;

FIG. 7B shows variations of a POC potential together with a source voltage V DD in a power-on mode;

FIG. 7C shows variations of an output of the reset circuit of FIG. 7A;

FIG. 8 shows a simple connection of two integrated circuits that operate independently of each other with their respective power sources;

FIG. 9 shows an integrated circuit coupled with a speaker;

FIG. 10A shows an example of a reset circuit that operates in a power-off mode;

FIG. 10B shows variations of a POC potential together with a source voltage V DD in the power-off mode; and

FIG. 10C shows an output of the reset circuit shown in FIG. 10 A.

This invention will be described in further detail by way of examples with reference to the accompanying drawings.

First Embodiment

FIG. 1 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a first embodiment of this invention. Herein, a capacitor CL and a p-type field effect transistor (FET) MP 1 are connected in series with respect to a source voltage V DD , wherein one end of the capacitor CL is grounded, and the other end corresponds to a terminal POC and is connected with the FET MP 1 , which acts as a resistor because its gate is grounded. A pair of p-type field effect transistors MP 2 and MP 3 are combined together to form a current mirror circuit. Specifically, the drain of the p-type FET MP 2 is connected to the terminal POC, while the drain of the p-type FET MP 3 is connected to the drain of an n-type FET MN 1 . Sources of the p-type FETs MP 2 and MP 3 are both connected with the source voltage V DD . The gate of the n-type FET MN 1 is connected with the source voltage V DD , and its source is grounded. Therefore, the n-type FET MN 1 acts as a resistor.

A pair of p-type FETs MP 4 and MP 5 are combined together to form a current mirror circuit. Specifically, the drain of the FET MP 4 is connected to a connection point between the FETs MP 3 and MN 1 as well as an input of an inverter I 2 . Both the gate and drain of the FET MP 5 are connected with the source voltage V DD . In addition, both the sources of the FETs MP 4 and MP 5 are connected to the terminal POC. The inverter 12 provides a reset signal at an output (OUT) thereof. All well regions of the FETs MP 1 to MP 5 are commonly connected. Alternatively, all the FETs MP 1 to MP 5 are formed on the common well region. The FETs MP 1 to MP 5 have prescribed on-resistances to satisfy the following inequalities.

MP 1 >>MP 3 >>MP 2

MP 4 >>MP 5

In the aforementioned configuration, a pair of the FETs MP 2 and MP 3 operate in a power-on (reset) mode, while a pair of the FETs MP 4 and MP 5 operate in a power-off (reset) mode.

Next, the operations of the power-on/off reset circuit of the first embodiment shown in FIG. 1 will be described in detail.

(1) Power-On Mode

The overall operation of the power-on/off reset circuit in a power-on mode will be described with reference to time charts shown in FIGS. 2A to 2 C. At time t 0 when electric power is applied to the circuitry, the source voltage V DD gradually increases in level as shown in FIG. 2 A. At this time, the capacitor is being charged via the FET MP 1 under the source voltage V DD , so that the potential of the terminal POC gradually increases as shown in FIG. 2 A. When the potential of the terminal POC exceeds the prescribed voltage of about 0.8 V, the FET MP 2 is turned on to provide a certain on-resistance, which is smaller than that of the FET MP 1 . Thereafter, the capacitor CL is being charged via the FET MP 2 , instead of the FET MP 1 , under the source voltage V DD . Therefore, the potential of the terminal POC further increases in accordance with the increasing of the source voltage V DD . In addition, a current flowing through the FET MP 2 correspondingly increases in accordance with the increasing of the source voltage V DD .

A certain current is forced to flow through the FET MP 3 in proportion to the current that flows through the FET MP 2 and is gradually increasing in accordance with the increasing of the source voltage V DD . Therefore, the input voltage ‘ND 1 ’ of the inverter I 2 gradually increases in level as shown in FIG. 2 B. In this case, the input voltage ND 1 increases in accordance with the increasing of the source voltage V DD , wherein it would be normally above the threshold of the inverter I 2 , so that the output of the inverter I 2 remains at a low (L) level, which is shown in FIG. 2 C.

After the source voltage V DD reaches the prescribed level, the potential of the terminal POC is continuously increasing. However, the current flowing through the FET MP 2 decreases in the progression of the charging of the capacitor CL because the source voltage V DD does not increase more than the prescribed level. This causes a reduction of the current flowing through the FET MP 3 , so that the input voltage ND 1 of the inverter I 2 starts decreasing. At time t 1 when the input voltage ND 1 becomes lower than the threshold of the inverter I 2 , the output of the inverter I 2 is inverted and becomes a high (H) level, which is shown in FIG. 2 C.

As described above, the power-on/off reset circuit of the first embodiment provides a reset signal (OUT) having a low level for a certain time period in the rise time of the source voltage V DD .

(2) Power-Off Mode

The overall operation of the power-on/off reset circuit in a power-off mode will be described with reference to time charts shown in FIGS. 3A to 3 C. Just before time t 0 when the electric power applied to the circuitry is cut off, the potential of the terminal POC substantially matches the source voltage V DD at its prescribed level, wherein both the FETs MP 2 and MP 5 are turned off so that the input voltage ND 1 of the inverter I 2 matches the ground level (see FIG. 3 B). As a result, the output of the inverter I 2 is at a high (H) level, which is shown in FIG. 3 C.

At time t 0 when the power supply is cut off, the source voltage V DD gradually decreases as shown in FIG. 3 A. In this case, as charges accumulated in the capacitor CL are gradually discharged, the potential of the terminal POC gradually decreases at a slow rate that is slower than the source voltage V DD (see FIG. 3 A). When the drain potential of the FET MP 5 becomes lower than its source potential by a certain value or more, a certain current is forced to flow from the terminal POC towards the power source (V DD ) via the FET MP 5 . Due to the current flowing through the FET MP 5 , its corresponding current flows through the FET MP 4 , so that the input voltage ND 1 gradually increases after time t 0 (see FIG. 3 B). That is, in accordance with the decreasing of the source voltage V DD , the input voltage ND 1 increases and then exceeds the threshold of the inverter I 2 at time t 1 . Hence, the output of the inverter I 2 is inverted and is turned to a low (L) level.

After time t 1 , the input voltage ND 1 further increases, while the potential of the terminal POC still gradually decreases. When the potential of the terminal POC reaches the prescribed level, the input voltage ND 1 is turned off from a peak and then starts decreasing. The input voltage ND 1 will become zero when charges accumulated in the capacitor CL are completely discharged.

As described above, the power-on/off reset circuit of the first embodiment provides a reset signal having a low level for a certain time period in the power-off mode.

The first embodiment is designed in such a way that the well regions of the transistors are not directly connected with the source voltage V DD and are placed in a floating state because of the following reason.

That is, when the source voltage V DD becomes lower than the potential of the terminal POC, in other words, when it becomes lower than Vf of the parasitic diode of the drain of the transistor, the parasitic diode should be turned on so that charges of the capacitor CL may be discharged towards the power source via the parasitic diode. To avoid such a problem, the well region of the transistor is placed in a floating state.

Second Embodiment

FIG. 4 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a second embodiment of the invention. The power-on/off reset circuit of the second embodiment comprises two sections, which provide reset signals in a power-on mode and a power-off mode respectively. That is, the first section of the power-on/off reset circuit shown in FIG. 4 comprises a p-type FET MP 1 , a capacitor CL, and an inverter I 1 , which provide a reset signal in a rise time of the source voltage V DD . Therefore, the first section is constituted similarly to the foregoing reset circuit shown in FIG. 7 A. The overall operation of the first section can be similarly explained with reference to time charts shown in FIGS. 5A to 5 C. That is, FIG. 5A shows variations of the potential of the POC terminal together with the source voltage V DD , and FIG. 5B shows the output of the inverter I 1 . That is, the inverter I 1 outputs a pulse-like signal in the rise time of the source voltage V DD . Such an output of the inverter I 1 is inverted by a NOR gate NR, which in turn provides a reset signal having a low (L) level (see FIG. 5C) in the rise time of the source voltage V DD .

The second section of the power-on/off reset circuit shown in FIG. 4 comprises p-type FETs MP 4 and MP 5 , and an n-type FET MN 1 , which provide a reset signal in a fall time of the source voltage V DD . Therefore, the second section is constituted similarly to the aforementioned circuitry of the first embodiment shown in FIG. 1, which provides a reset signal in the fall time of the source voltage V DD . A signal (ND 1 ) at a connection point between the FETs MP 4 and MN 1 is inverted by the NOR gate NR, which in turn provides a reset signal in the fall time of the source voltage V DD .

Third Embodiment

FIG. 6 is a circuit diagram showing the configuration of a power-on/off reset circuit in accordance with a third embodiment of the invention. Like the second embodiment, the power-on/off reset circuit of the third embodiment comprises two sections, which provide reset signals in a power-on mode and a power-off mode respectively. That is, the first section of the power-on/off reset circuit shown in FIG. 6 comprises p-type FETs MP 1 , MP 2 , and MP 3 , an n-type FET MN 1 a , a capacitor CL, and an inverter I 2 a , which provide a reset signal in a rise time of the source voltage V DD . Therefore, the first section is constituted similarly to the aforementioned first embodiment shown in FIG. 1, specifically, the circuitry comprising the FETs MP 1 , MP 2 , MP 3 , and MN 1 , capacitor CL, and inverter I 2 , which provide a reset signal in the rise time of the source voltage V DD .

The second section of the power-on/off reset circuit shown in FIG. 6 comprises p-type FETs MP 4 and MP 5 , an n-type FET MN 1 b , and an inverter I 2 b , which provide a reset signal in a fall time of the source voltage V DD . Therefore, the second section is constituted similarly to the aforementioned first embodiment shown in FIG. 1, specifically the circuitry comprising the FETs MP 4 , MP 5 , MN 1 , and inverter I 2 , which provides a reset signal in the fall time of the source voltage V DD . Outputs of the inverters 12 a and 12 b are supplied to an OR gate (OR), which in turn provides a reset signal for both the rise time and fall time of the source voltage V DD .

In the second and third embodiments, the well regions of the transistors are commonly connected together in a floating state. Alternatively, these transistors are formed on the common well region.

In summary, this invention provides a power-on/off reset circuit that contains a power-on reset circuit and a power-off reset circuit. Specifically, the power-on reset circuit provides a reset signal that is turned on in response to the on-timing of the source voltage and is then turned off when the potential of a capacitor reaches the prescribed level. The power-off reset circuit provides a reset signal that is turned on when the potential of the capacitor decreases to a certain value after the off-timing of the source voltage and is sustained until the source voltage becomes substantially zero. Therefore, the power-on/off reset circuit of this invention can provide reset signals for both of the on-timing and off-timing of the source voltage.

As this invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.