Voltage output differential (VOD) correction circuit for differential drivers

The present invention relates generally to electrical circuits and more particularly to current driven differential drivers.

In a typical communication system, inter-chip high-speed communication is generally limited by the performance of driver and receiver circuits at the interface of communicating chips. Standards have been established for high-speed signal handling applications including, for example, low voltage differential signaling (LVDS) and positive emitter-coupled logic (PECL). These standards enable the design of high-speed systems with minimum power dissipation and low electromagnetic interference (EMI). However, inter-chip high-speed communication is still limited by the performance of driver and receiver circuits at the interface of these devices. The LVDS TIA/EIA-644 standard specifies an output voltage through 100 Ohms to be within 247 mv to 454 mv. This provides sufficient signal amplitude for transforming data without overdriving the connected receiver.

One limitation involves a condition known as low voltage output differential (VOD). The VOD of a differential driver is the voltage differential between the two components of the differential output signal. In systems employing LVDS, the VOD is designed to be on the order of about 400 mv. In LVDS, the lower voltage output of the differential pair is typically 1.0 V while the higher output voltage is typically 1.4 V. The difference between the two is about 400 mv while the average of the two is the common mode voltage, V CM . For the above example, V CM is about 1.2V. The VOD is created by steering a constant current from one output terminal though a standard 100 ohm load resistor to the other output terminal. Current generators are typically used to establish the output currents, I SOURCE and I SINK at the two respective output terminals. When process variations cause output current sources to provide I SOURCE and I SINK values that are below specified levels, then the resulting VOD will be low. A low VOD reduces the noise immunity within the LVDS system and can impact total system performance. Low output currents often result from process variations in resistors that are used to determine the current values. As process limitations can produce variations of plus or minus 20% in resistor values, the corresponding output currents are also subject to plus or minus 20% variations that result in similar variations of VOD.

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

The present invention relates to system and methods for compensating the Voltage Output Differential (VOD) of current driven driver circuits (e.g., LVDS driver circuits) to maintain a desired VOD during driver operation. The system and methods provide for monitoring internal circuit performance and correcting for variations in output current supplied to maintain a desired VOD between the two differential output signals. The present invention provides for comparing the voltage of a representative signal that is based on the VOD with a reference signal that is set to a desired voltage level based on a desired VOD. By determining whether the representative voltage level is higher, equal to, or lower than the desired reference level, balanced adjustments may be made to at least one of the output current source level and the output current sink level to alter the VOD. Balancing the adjustment to the two current sources maintains the existing desired common mode voltage (V CM ). A balanced increase in the source and sink currents at the output results in an increased, VOD while a balanced decrease in the source and sink currents results in a decrease in VOD.

In one aspect of the present invention, a representative DC signal of the VOD is compared with a reference signal that is set to a desired level. The representative DC signal varies in voltage level by a known offset. The reference signal is set to a value equal to the desired output voltage level plus the known offset. A common mode voltage (V CM ) regulator is employed to maintain V CM equal to the average of the two output voltage levels. Since V CM is known, monitoring either the higher differential output voltage or the lower differential output voltage is equivalent to monitoring the VOD. If VOD is low, the output source current and/or the output sink current is increased such that VOD is restored to the desired level. This is accomplished by increasing (e.g., adding) current to a current source that is reflected to at least one of the source current and sink current until the desired VOD is achieved. Similarly, if VOD is high, one or both of the output source current and output sink current are decreased such that VOD is restored to the desired level. This is accomplished by decreasing the current to a current source that is reflected to one or both the source current and the sink current until the desired VOD is achieved.

The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

FIG. 1 illustrates a block diagram of a driver system in accordance with an aspect of the present invention.

FIG. 2 illustrates a block diagram of an alternate driver system in accordance with another aspect of the present invention.

FIG. 3 illustrates a functional block diagram of a differential driver system with VOD regulation in accordance with an aspect of the present invention.

FIG. 4 illustrates an electrical schematic of current generator in accordance with an aspect of the present invention.

FIG. 5 illustrates a VOD correction circuit for low VOD in accordance with an aspect of the present invention.

FIG. 6 illustrates a VOD correction circuit for both high VOD and low VOD in accordance with an aspect of the present invention.

FIG. 7 illustrates a block diagram of a methodology for increasing low VOD in accordance with an aspect of the present invention.

FIG. 8 illustrates a block diagram of a methodology for decreasing high VOD in accordance with an aspect of the present invention.

The present invention provides systems and methodologies to correct voltage output differential (VOD) variations that result from process variations in current driven drivers, such as Low Voltage Differential Signal (LVDS) drivers. VOD variations result when the resistance values of resistors that determine reference currents vary as a function of the manufacturing process. The reference currents are reflected through a series of current mirrors to create output source and output sink currents that drive a specified load. The voltage created by the output currents that flow through the load provides the VOD. The VOD is the difference in voltage between the high and low output signals of a differential driver pair. The present invention utilizes a compensation device (e.g., differential comparator circuit) that compares an internal DC signal that is based on the VOD to an established reference voltage level, and generates a current stimulus that modifies current through the driver outputs to maintain a desired VOD. The internal DC signal has a known relationship to the VOD.

In one aspect of the invention, a compensation or correction circuit is employed that determines the results of a comparison of an internal DC signal based on the VOD and an established reference voltage level, and provides a correction current that will either be added, or subtracted, to a reference current that is reflected through a series of current mirrors to create an adjustment in one or both the source and sink currents of the output of the driver. Balancing the adjustment between the source and the sink currents maintains the established common mode voltage (V CM ). V CM is the average of the high and low differential outputs.

FIG. 1 is a block diagram of a driver system 10 that regulates the VOD of the differential outputs in accordance with an aspect of the present invention. The driver system 10 consists of a differential driver 12 , a nominal current reference generator 14 , and a VOD current compensator 16 . The nominal current reference generator 14 generates reference current signals that in part determine the output currents I SOURCE and I SINK in addition to regulating the common mode voltage (V CM ) of the differential driver 12 . The reference current signals include I SOURCENOM , I SINKNOM and I CNTRLNOM . The differential driver 12 utilizes the reference current signal I SOURCENOM to generate I SOURCE and the reference current signal I SINKNOM to generate I SINK . The differential driver 12 utilizes the reference current signal I CNTRLNOM to modify I SOURCE and I SINK to sustain a desired V CM voltage level

The differential driver 12 receives a singled ended input signal (A), and converts it to a pair of differential output signals Y and YZ. The differential driver 12 drives output currents I SOURCE and I SINK through a load resistance (R LOAD ) that is external to the driver system 10 . The voltage differential across the output nodes Y and YZ is known as the voltage output differential (VOD). The VOD current compensator 16 determines if the resulting VOD is low. If the resultant VOD is low, the VOD current compensator 16 adds current that results in an increase to at least one of the output currents I SOURCE and I SINK . If the resultant VOD is high, the VOD current compensator 16 subtracts current that results in a decrease to at least one of the output currents I SOURCE and I SINK It is to be appreciated that although I SOURCE is illustrated as flowing through top terminal Y and I SINK is illustrated as flowing through the bottom terminal YZ, the direction I SOURCE can be through terminal YZ and the direction of I SINK can be through terminal Y. The direction that the current I SOURCE and I SINK are steered determines whether the output signal is a logic high or a logic low. In the example of FIG. 1, the direction of I SOURCE is illustrated as flowing through terminal Y and the direction of I SINK is illustrated as flowing through terminal YZ indicating a logic high.

FIG. 2 is a block diagram of an alternate driver system 50 that regulates the VOD of the differential outputs in accordance with another aspect of the present invention. The driver system 50 consists of a differential driver 52 , a nominal current reference generator 54 , and a VOD current adder/subtractor 56 . The nominal current reference generator 54 generates reference current signals that in part determine the nominal output currents I SOURCE and I SINK in addition to regulating the common mode voltage (V CM ) of the differential driver 52 . The reference current signals include I SOURCENOM , I SINKNOM and I CNTRLNOM . The differential driver 52 utilizes the reference current signal I SOURCENOM to generate I SOURCE and the reference current signal I SINKNOM to generate I SINK . The differential driver 52 utilizes the reference current signal I CNTRLNOM to modify I SOURCE and I SINK to sustain a desired V CM voltage level,

The differential driver 52 receives a singled ended input signal (A), and converts it to a pair of differential output signals Y and YZ. The differential driver 52 drives output currents I SOURCE and I SINK through a load resistance (R LOAD ) that is external to the driver system 50 . The VOD current adder/subtractor 56 determines if the resulting VOD is low or high. If the resultant VOD is low, the VOD current adder/subtractor 56 adds current that results in an increase to at least one of the output currents I SOURCE and I SINK . If the resultant VOD is high, the VOD current adder/subtractor 56 subtracts current that results in a decrease to at least one of the output currents I SOURCE and I SINK . In the example of FIG. 2, the direction of I SOURCE is illustrated as flowing through terminal YZ and the direction of I SINK is illustrated as flowing through terminal Y indicating a logic low. It is to be appreciated that the adder portion or the subtractor portion of the VOD current adder/subtractor 56 can be implemented without the other if desired for a particular implementation.

FIG. 3 illustrates a differential driver system 100 that includes VOD regulation in accordance with an aspect of the present invention. In system 100 , input signal A is a single ended input such as a TTL input provided to an input state 102 . It is to be appreciated that signal A can be any singled ended or rail-to-rail input signal. The input stage 102 receives input signal A and provides signal A and signal AZ (the inverse of signal A) to an output stage 106 . The output stage 106 also receives currents I SOURCEREF and I SINKREF from a Source/Sink Current Controller 112 . The output stage 106 , based on the logic levels of the inputs received, drives output currents I SOURCE and I SINK from terminals Y and YZ to an external load. The output currents I SOURCE and I SINK are derived from the currents I SOURCEREF and I SINKREF from the Source/Sink Current Controller 112 . The VOD is measured across terminals Y and YZ as a function of the output currents I SOURCE and I SINK driven through external load R LOAD .

The output stage 106 also provides two reference signals, V CM and V REFVOD , that are used in part to control the output currents I SOURCE and I SINK V CM is the common mode voltage that represents the average of the voltage level between terminal Y and ground and between terminal YZ and ground. V CM is provided by the output stage 106 to a V CM regulator 118 and is used in keeping I SOURCE and I SINK balanced such that the desired V CM is achieved. The other output signal, V REFVOD , provides a signal that is a function of VOD. V REFVOD is utilized by a current/adder subtractor 132 in maintaining VOD at an appropriate level.

The common mode voltage is controlled by the V CM Regulator 118 . The V CM regulator 118 receives signal V CM from the output stage and compares V CM with known reference signal V BG (Bandgap Voltage). V BG is set to be equal to the desired value of V CM . In the case of an LVDS driver, V BG is typically set equal to about 1.2 volts. Another input to the V CM regulator 118 is a current, I CNTRL which originates in a VCM control 124 . Under nominal operating conditions, I CNTRL will be equally divided into two currents, I SOURCEDELTA and I SINKDELTA which are output from V CM regulator 118 . However, if VCM is less than V BG , then V CM is low and must be adjusted to a higher level. The V CM regulator 118 enables this result by shifting the division of I CNTRL between I SOURCEDELTA and I SOURCEDELTA to increase the current I SOURCEDELTA and decrease the current I SINKDELTA . Similarly, if V CM is greater than V BG , then V CM is high and must be adjusted to a lower level. The VCM regulator 118 enables this result by shifting the division of I CNTRL between I SOURCEDELTA and I SOURCEDELTA to decrease the current I SOURCEDELTA and increase the current I SINKDELTA .

I SOURCEDELTA and I SINKDELTA are inputs to the Source/Sink Current Controller 112 . The Source/Sink Current Controller 112 combines nominal reference currents, I SOURCENOM and I SINKNOM , with incremental delta currents to form reference currents, I SOURCEREF and I SINKREF which are reflected by the output stage 106 as currents I SOURCE and I SINK . Source/Sink Current Controller 112 combines I SOURCENOM with I SOURCEDELTA to form I SOURCEREF . Remembering that I SOURCEDELTA is increased when V CM is low, I SOURCEREF will correspondingly increase and result in an increased current being reflected to I SOURCE . Similarly, Source/Sink Current Controller 112 combines I SINKNOM with I SINKDELTA to form I SINKREF . Remembering that I SINKDELTA is decreased when V CM is low, I SINKREF will correspondingly decrease and result in a decreased current being reflected to I SINK . Increasing I SOURCE and decreasing I SINK serves to raise the level of V CM .

A nominal current reference generator 128 generates three reference currents I SOURCENOM , I SINKNOM and I CNTRLNOM . The source/sink current control 112 utilizes the reference current signal I SOURCENOM to generate I SOURCE and the reference current signal I SINKNOM to generate I SINK . The V CM control 124 utilizes the reference current signal I CNTRLNOM to generate I CNTRL . I CNTRL is output from the V CM control 124 to the VCM Regulator 118 . An increase in I CNTRL serves to increase the VOD observed across the output terminals Y and YZ. This is accomplished as an increase in I CNTRL results in an increase to at least one of I SOURCEDELTA and I SINKDELTA which in turn increases at least one of I SOURCEREF and I SINKREF . An increase in at least one of I SOURCEREF and I SINKREF results in an increase in at least one of I SOURCE and I SINK causing an increase VOD across terminals Y and YZ while still maintaining a constant V CM .

I VOD+ and I VOD− are determined by the Current Adder/Subtractor 132 . The Current Adder/Subtractor compares a signal, V REFVOD , related to VOD, to a known reference input V REF . V REF is set to a predetermined value that corresponds to the expected value of V REFVOD for the desired level of VOD. If VOD is low, then V REFVOD will be low and the Current Adder/Subtractor 132 creates an adder current I VOD+ which is output to the VCM control 124 and results in an increase to I CNTRL . Similarly, if VOD is high, the V REFVOD will be high and the Current Adder/Subtractor 132 creates a subtractor current I VOD− which is output to the VCM control 124 and results in a decrease to I CNTRL . As described above, the present invention adjusts the output currents I SOURCE and I SINK in order to maintain a desired VOD. This is accomplished by comparing a signal based on VOD to a known reference and correspondingly adjusting the output currents to compensate for either a low or high VOD.

FIG. 4 is an electrical schematic of a current generator 150 that is used to generate reference currents employed in a differential driver in accordance with an aspect of the present invention. The current generator 150 includes a current reference 154 formed from transistor P 3 , transistor N 4 and resistor R 1 to generate a reference current I REF . In FIG. 4, current I REF is established based in part on the resistance value R 1 . The resistance value of R 1 will vary on the order of plus or minus 20% based on process limitations. As a result, I REF is subject to similar variations of plus or minus 20%. In current generator 150 , P 3 is coupled in a current mirror configuration with P 4 , P 5 , and P 6 such that the current I REF is mirrored to three reference currents I SOURCENOM , I SINKNOM and I CNTRLNOM , which are output through terminal pins CHP, CHN and CHCNTRL, respectively. Since I REF is subject to variations of plus or minus 20%, the three nominal current references will also be subject to similar variations of plus or minus 20%.

I SOURCENOM , I SINKNOM and I CNTRLNOM are utilized in differential driver circuit 200 of FIG. 5 to, in part, establish the nominal parameters at the output of the differential driver, (e.g. I SOURCE , I SINK , V CM and VOD). Without some type of feedback and adjustment, the output currents I SOURCE , I SINK and output voltages VOD and V CM will be subject to similar variations. Referring again to FIG. 4, the current generator 150 includes a differential comparator 152 comprised of transistor P 1 , P 2 , N 1 , N 2 and N 3 . The differential comparator 152 compares a voltage at the resistor RI with a bandgap reference voltage V BG , which is substantially equal to the common mode voltage V CM (e.g., 1.2 Volts for LVDS drivers). Transistor N 1 is a bias transistor that sets the current of the differential comparator 152 and is controlled by a signal V B . Transistors P 1 and P 2 are active loads for the differential comparator 152 , while transistor N 2 and N 3 form the differential pair of the differential comparator 152 . The differential comparator 152 adds current through N 4 to I REF in the event that the voltage across R 1 is below V BG .

FIG. 5 illustrates an electrical schematic of a differential driver circuit 200 in accordance with an aspect of the present invention. The differential driver circuit 200 provides for increasing VOD in response to a low VOD condition. This particular implementation provides for increasing the level of VOD when expected process variations cause deviations from nominal conditions, such that the nominal VOD level may be below a desired VOD level. Dashed lines in FIG. 5 are employed to help identify functionality that is implemented in a designated portion of the circuit. A data input stage 210 is provided that comprises MOSFET devices MP 89 and MN 90 . Input stage 210 receive input signal A at the gate of the two MOSFET devices MP 89 and MN 90 . MP 89 and MN 90 are coupled in series together to form an inverter circuit that provides a signal AZ that is the inverse of A. Signal A and AZ are are provided to an output stage 280 .

The output stage 280 comprises MOSFET devices MP 38 , MP 41 , MN 37 , MN 42 , MP 55 , MN 12 , Resistors, R 111 , R 112 , R TOP and Capacitor C TOP . MP 38 , MP 41 , MN 37 and MN 42 are coupled together in an H configured crosspoint switch that steers the output current to output Y or YZ based upon signals A and AZ. The current which flows between outputs Y and YZ generates the VOD when it flows through an external load of a specified value (e.g., 100 ohms). MOSFET device MP 55 is coupled to MP 38 and MP 41 and provides current I SOURCE which flows through either MP 41 to output YZ or through MP 38 to output Y depending on the logic levels of signals A and AZ. MP 55 and MOSFET device MP 8 form a current mirror such that current I SOURCE is determined by a current I SOURCEREF (I 5 ) that flows through MP 8 and a source current controller 240 .

Similarly, MOSFET device MN 12 is coupled to MN 37 and MN 42 and provides current I SINK from output terminal Y through MN 37 or from output terminal YZ through MN 42 depending upon the logic levels of signals A and AZ. MN 12 and MOSFET device MN 9 form a current mirror such that current I SINK is determined by current I SINKREF (I 3 ) that flows through MN 9 in a sink current controller 242 . R 111 and R 112 are resistors of substantially equal value. R 111 is coupled to output Y and R 112 , while R 112 is coupled to R 111 and output YZ. One side of R TOP is coupled to the drain of MP 55 and the sources of MP 38 and MP 41 and the other side of R TOP is coupled to C TOP . C TOP is also coupled to ground. R TOP and C TOP serve to filter out AC ripple or noise on an otherwise DC signal. The common node of R TOP and C TOP provides a voltage reference signal V REFVOD . V REFVOD is a signal which differs in voltage by a known amount (the voltage drop across one MOSFET device) from the higher of the two voltages at outputs Y and YZ. As will be discussed, V CM is controlled to a known value, therefore, the DC component of V REFVOD can be determined to be equal to about V CM +½VOD+the voltage drop across one MOSFET device. V REFVOD is provided by the output stage 220 to a current adder 260 . Voltage signal V CM originates at the node which couples R 111 and R 112 together and represents the midpoint of the voltage measured between output terminals Y and YZ.

A V CM regulator 230 functions to alter currents I SOURCE and I SINK when necessary to keep V CM at a desired level (e.g., 1.2V). The V CM regulator 230 comprises MOSFET devices MP 13 , MP 14 , MN 15 , MN 16 and MP 19 . MPl 9 is coupled in a current mirror configuration with MOSFET device MP 1 of a V CM control 270 . MP 19 provides current I CNTRL that is mirrored from I 6 that flows through MP 1 . MP 13 and MP 14 are coupled together in a comparator configuration that divides I CNTRL into Delta I SOURCE (I 8 ) and Delta I SINK (I 7 ). The division of current is based on a comparison of V CM (coupled to MP 13 ) and V BG (coupled to MP 14 ). V BG is set to a known, stable voltage level substantially equal to the desired voltage level for V CM . The comparator divides I CNTRL such that Delta I SOURCE (I 8 ) is increased and Delta I SINK (I 7 ) is decreased when V CM is low. Delta I SOURCE (I 8 ) is decreased and Delta I SINK (I 7 ) is increased when V CM is high. Delta I SINK (I 7 ) flows though MN 9 of the sink current controller 242 that is configured as a current mirror with MN 12 of the output stage 280 . The change in Delta I SINK (I 7 ), changes I SINKREF (I 3 ) in MN 9 which is reflected as a change in I SINK through MNI 12 . Similarly, Delta I SOURCE (I 8 ) flows through MN 15 . MN 15 and MN 16 are configured as current mirrors such that a change in Delta I SOURCE (I 8 ) reflects as a change in current through MN 16 which in turn changes the current I SOURCEREF (I 5 ) through MP 8 of the source current controller 240 which is configured as a current mirror with MN 55 of the output stage 280 . The change in Delta I SOURCE (I 8 ) adds to I SOURCEREF (I 5 ) in MP 8 that is reflected as a change in I SOURCE through MP 55 .

The source current controller 240 serves to generate I SOURCE by combining Nominal I SOURCE (I 1 ) and Delta I SOURCE (I 8 ), while the sink current controller 242 serves to generate I SINKREF by combining Nominal I SINK (I 3 ) with Delta I SINK (I 8 ). The source current controller 240 comprises MOSFET devices MN 8 , MN 11 , MN 5 , MN 6 and MP 8 . The sink current controller 242 comprises MOSFET devices MN 10 and MN 9 . Nominal I SINK (I 3 ), Nominal I SOURCE (I 1 ), and Nominal I CNTRL (I 2 ) originate in a nominal current reference generator such as described in FIG. 4 .

MN 9 and MN 10 are coupled together in series. Nominal I SINK (I 3 ) flows through MN 10 and combines with Delta I SINK (I 7 ) to form I SINKREF that flows through MN 9 . Since MN 9 and MN 12 (output stage 280 ) are coupled together in a current mirror configuration, I SINKREF is reflected as I SINK through MN 12 . MN 8 is coupled in series with MN 11 and MN 5 is coupled in series with MN 6 . Additionally, MN 8 is coupled together with MN 5 in a current mirror configuration and, similarly, MN 11 and MN 6 are coupled together in a current mirror configuration. Nominal I SOURCE (I 1 ) flows through MN 8 and MN 11 such that a mirrored current, I 5 also flows through MN 5 and MN 6 . MP 8 serves to combine I 5 and a current mirrored from Delta I SOURCE (I 8 ), to form I SOURCEREF . Since MP 8 and MP 55 (output stage 280 ) are coupled together in a current mirror configuration, I SOURCEREF is reflected as I SOURCE through MP 55 .

The current adder circuit 260 monitors a voltage related to VOD and provides a stimulus when VOD is low that results in an increase to both I SOURCE and I SINK , which thereby increases VOD. The current adder circuit 260 is a differential comparator and comprises MOSFET devices MPO, MN 1 , MP 2 , MP 3 , MN 7 and MN 14 . Signal V GATE controls the MOSFET device MP 14 , which acts as a bias transistor. MN 1 is coupled to MP 2 and MN 7 is coupled to MPO. MN 1 and MN 7 are coupled together in a comparator configuration and MPO and MP 2 serve as active loads for the comparator. MP 3 is coupled to MN 7 and to the current mirror pair MN 2 and MN 0 (VCM Control 270 ) such that I VOD+ adds to the current flowing through the current mirror pair MN 2 and MN 0 . The input to the gate of MN 1 is V REFVOD which varies in direct relationship to VOD. The input to MN 7 is V REF . V REF is established to be equal to the desired level of V REFVOD for the desired level of VOD.

If VOD is at the desired voltage level, then V REFVOD and V REF are equal. In this condition, MN 7 and MN 1 provide equal components of current I 4 . If VOD is low, I VOD+ will increase driving V REFVOD substantially equal to V REF . The result is that the component of I 4 provided by MN 7 will increase and the component of I 4 provided by MN 1 will decrease. As a result, the gate of MP 3 will be pulled lower and I VOD+ will further increase through MP 3 . I VOD+ is provided to the V CM control 270 .

The V CM control 270 responds to I VOD+ with a stimulus that will result in an increase in VOD. The V CM control 270 comprises MOSFET devices MP 1 , MNO, MN 2 , MN 3 , and MN 4 . MN 3 is coupled in series with MN 2 and MP 1 is coupled in series with MN 0 and MN 4 . Additionally, MN 3 is coupled together with MN 4 in a cascode mirror configuration and, similarly, MN 0 and MN 2 are coupled together in a current mirror configuration. I CNTRLNOM (I 2 ) flows through MN 3 to MN 2 where MN 2 serves to combine I CNTRLNOM (I 2 ) and IVOD+into a current that is reflected to MN 0 as I 6 . I 6 flows through MN 4 and MP 1 where it is reflected to I CNTRL through MP 19 of the VCM regulator 230 . The change in I CNTRL will result in a balanced change to both Delta I SOURCE (I 8 ) and Delta I SINK (I 7 ). These current changes will be reflected as discussed before and will result in a balanced increase to both I SOURCE and I SINK such that VOD will be appropriately increased or decreased while maintaining the level of V CM .

FIG. 6 illustrates an electrical schematic of the differential driver circuit 300 that includes a current adder/subtractor circuit 290 in accordance with an aspect of the present invention. FIG. 6 illustrates a differential driver circuit similar to the differential driver circuit 200 of FIG. 5, but provides for decreasing VOD in response to a high VOD condition in addition to increasing VOD in response to a low VOD condition. The differential driver circuit 300 includes similar components as that described with respect to the differential driver circuit 200 (FIG. 5) except that three additional MOSFET devices MP 4 , MN 17 and MN 18 have been added to the current adder circuit 260 of FIG. 5 to provide the current/adder subtractor circuit 290 of FIG. 6 . These three MOSFET devices implement the ability to subtract current from the current I CNTRL provided to the VCM regulator 230 .

The current adder/subtractor circuit 290 monitors a voltage related to VOD and provides a stimulus when VOD is low that results in an increase to both I SOURCE and I SINK , which thereby increases VOD. Similarly, when VOD is high, the current adder/subtractor circuit 290 provides a stimulus that results in a decrease to both I SOURCE and I SINK , which thereby decreases VOD. The current adder/subtractor circuit 290 comprises MOSFET devices MP 0 , MN 1 , MP 2 , MP 3 , MP 4 MN 7 , MN 14 , MN 17 , and MN 18 . The adder portion of the current adder/subtractor circuit 290 has been described in FIG. 5 and therefore a description of the adder portion will be omitted for the sake of redundancy.

The subtractor portion of the current adder/subtractor circuit 290 includes the addition of MP 4 coupled to MN 1 and to MN 18 , which is coupled to MN 17 in a current mirror configuration such that the current flowing through MN 17 is reflected to provide I VOD− . MN 17 is coupled to current mirror pair MN 2 and MN 0 (VCM control 270 ) such that the current through MN 17 reduces the currents through the current mirror pair MN 2 and MN 0 . The input to the gate of MN 1 is V REFVOD (filtered) which varies in direct relationship to VOD. The input to MN 7 is V REF . V REF is established to be equal to the desired level of V REFVOD for the desired level of VOD. If VOD is at the desired voltage level, then V REFVOD and V REF are equal. In this condition, MN 7 and MN 1 provide equal components of current I 4 and the voltage level of the gates of MP 3 and MP 4 are such that current I VOD+ is zero and I VOD− is zero.

If VOD is low, then V REFVOD will be less than V REF . The result is than the component of I 4 provided by MN 7 will increase and the component of I 4 provided by MN 1 will decrease. As a result, the gate of MP 3 will be pulled lower and IVOD+will increase through MP 3 . I VOD+ is provided to the VCM control 270 . Similarly, the gate of MP 4 will rise and I VOD− will remain zero. If VOD is high, then V REFVOD will be greater than V REF . The result is than the component of I 4 provided by MN 1 will increase and the component of I 4 provided by MN 7 will decrease. As a result, the gate of MP 4 will be pulled lower and current will decrease through MP 4 . The gate of MP 3 will rise and I VOD+ will remain zero. I VOD− is provided to the VCM control 270 through the current mirror pair MN 18 , MN 17 .

The VCM control 270 responds to I VOD+ with a stimulus that will result in an increase in VOD and similarly responds to I VOD− such with a stimulus that will result in a decrease in VOD. The VCM control 270 comprises MOSFET devices MP 1 , MNO, MN 2 , MN 3 , and MN 4 . MN 3 is coupled in series with MN 2 . MP 1 is coupled in series with MN 0 and MN 4 . Additionally, MP 3 is coupled together with MN 4 in a current mirror configuration and, similarly, MN 0 and MN 2 are coupled together in a current mirror configuration. I CNTRLNOM (I 2 ) flows through MN 3 to MN 2 where MN 2 serves to combine I CNTRLNOM (I 2 ), I VOD− and I VOD+ into a current that is reflected to MN 0 as I 6 . I 6 flows through MN 4 and MP 1 where it is reflected to I CNTRL through MP 19 of the VCM Regulator 230 . The change in I CNTRL will result in a balanced change to both Delta I SOURCE (I 8 ) and Delta I SINK (I 7 ). These current changes will be reflected as discussed before and will result in a balanced increase to both I SOURCE and I SINK such that VOD will be appropriately increased or decreased while maintaining the level of V CM .

In view of the foregoing structural and functional features described above, methodologies in accordance with various aspects of the present invention will be better appreciated with reference to FIGS. 7-8. While, for purposes of simplicity of explanation, the methodologies of FIGS. 7-8 is shown and described as executing serially, it is to be understood and appreciated that the present invention is not limited by the illustrated order, as some aspects could, in accordance with the present invention, occur in different orders and/or concurrently with other aspects from that shown and described herein. Moreover, not all illustrated features may be required to implement a methodology in accordance with an aspect the present invention. Further, the methodologies of FIGS. 7-8 may be combined and implemented together.

FIG. 7 illustrates one particular methodology for implementing a VOD correction of a current driver device (e.g., LVDS) in accordance with an aspect of the present invention. The methodology begins at 300 , where a signal that is representative of an actual VOD level is monitored. The signal can be monitored at a location of the driver that the voltage is relatively constant during operation. The representative signal will then have a know relationship to the VOD of the driver device. The methodology then proceeds to 310 . At 310 , the representative signal is compared to a reference signal that is set to be equal to the level that the signal representative of VOD will be if VOD is at the desired level. At 320 , the comparison is employed to determine if the VOD is low or below a desired VOD. If at 320 , the two signals are equal, then VOD is not low (NO) and the method returns to 300 to continue to monitor the representative signal. If at 320 , the representative signal is less than the reference signal, then VOD is low (YES) and the method proceeds to 330 .

At 330 an incremental current is generated which is added at 340 to the nominal current that determines the nominal VOD to provide an increased current. At 350 , the increased current is reflected through to a VCM regulator. At 360 , the reflected increased current is equally divided and added to reference currents that determine the output source current and output sink current. At 370 , the increased reference currents are reflected to the output source and output sink currents. The method then returns to 300 where the signal that is representative of VOD will continue to be monitored.

FIG. 8 illustrates another methodology for implementing a VOD correction for a current driver device (e.g., LVDS) in accordance with an aspect of the present invention. The methodology begins at 400 , where a signal that is representative of an actual VOD level is monitored. The signal can be monitored at a location of the driver that the voltage is relatively constant during operation. The representative signal will then have a know relationship to the VOD of the driver device. The methodology then proceeds to 410 . At 410 , the representative signal is compared to a reference signal that is set to be equal to the level that the signal representative of VOD will be if VOD is at the desired level. At 420 , the comparison is employed to determine if the VOD is high or above a desired VOD. If at 420 , the two signals are equal, then VOD is not high (NO) and the method returns to 400 to continue to monitor the representative signal. If at 420 , the representative signal is higher than the reference signal, then VOD is high (YES) and the method proceeds to 430 .

At 430 an incremental current is generated which is subtracted at 440 from the nominal current that determines the nominal VOD to provide a decreased current. At 450 , the decreased current is reflected through to a V CM regulator. At 460 , the reflected decreased current is equally divided and subtracted from the reference currents that determine the output source current and output sink current. At 470 , the decreased reference currents are reflected to the output source and output sink currents. The method then returns to 400 where the signal that is representative of VOD will continue to be monitored.

What has been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.