Single mask trench fred with enlarged Schottky area

Fast recovery diodes are well known. These devices frequently integrate P-N junctions and Schottky diodes in a common die. Trench Schottky diodes are also well known and are shown in U.S. Pat. No. 5,365,102 to Baliga, and in application Ser. No. 10/193,783 filed Jul. 11, 2002 entitled TRENCH SCHOTTKY in the names of Kohji Andoh and Davide Chiola, which is assigned to the assignee of the present invention.

This invention relates to fast recovery diodes and more specifically relates to a single mask process for the manufacture of a fast recovery diode with an increased Schottky diode area with a trench topology.

The manufacture of fast recovery diodes with trench topology now requires the use of plural mask steps and have a relatively small Schottky diode area relative to the die or chip area.

It would be desirable to provide a fast recovery diode having an enlarged Schottky area for a lower forward voltage drop and to make the device with a reduced number of masks steps, preferably a single critical step.

In accordance with the invention a novel fast recovery diode is made with a single critical mask step which defines a trench etch region. A locos-type process is also employed to enable the selective removal of nitride in the active area before metallization. In the resulting device, the bottoms of the trenches receive a local P type diffusion, producing small P-N junctions at each trench, while the full trench walls and the mesas between trenches receive a Schottky-forming metal.

FIG. 1 shows a small portion of a wafer in which a plurality of die are simultaneously processed, after an optional N + blanket diffusion and the growth of a field oxide.

FIG. 2 shows the wafer of FIG. 1 after the deposition of an Si 3 N 4 (nitride) layer atop the field oxide and the formation of a photoresist layer and the processing of the layer in the single mask step of the invention.

FIG. 3 shows the wafer of FIG. 2 after a nitride etch, a trench etch, and a P type species implant into the bottom of the trenches.

FIG. 4 shows the wafer of FIG. 3 after a resist strip and the P implant drive.

FIG. 5 shows the wafer of FIG. 4 after an oxide etch which completely clears the oxide in the active area, but only partially removes the oxide in the termination area.

FIG. 6 shows the wafer of FIG. 5 after metal deposition.

Referring first to FIG. 1, there is shown a very small portion of the top of a silicon wafer 10 . The wafer may be a wafer of any desired thickness with an N + body (not shown) and an N-epitaxial layer which will receive the various junctions. While the description of the invention in FIGS. 1 to 6 describes an N type wafer body, the invention can also be carried out with a P type body.

The first step shown in FIG. 1 is the optional blanket implant of an N type species to form N + region 11 . This implant, which may be an arsenic implant of a dose 5E14/cm 2 can be eliminated from the process. Thereafter, a field oxide 12 is thermally grown atop wafer 10 to a thickness of about 7000 Å.

The next step is shown in FIG. 2 and is the deposition of a Si 3 N 4 (nitride) layer 13 atop the oxide layer 12 . Thereafter, a conventional photoresist layer 14 is deposited atop the nitride layer 13 .

A single mask step is then carried out in which the photoresist 14 is patterned and a plurality of slots, including slots 15 , 16 , 17 are formed in the photoresist. Slots 15 , 16 and 17 are 3 of a large number of parallel slots, which may have a stripe or cellular topology, as desired. The slots shown are in a very small portion of wafer 10 , with slot 15 defining a portion of the termination region of a single die or chip in the wafer, and slots 16 and 17 defining a small portion of the active region for that die.

As next shown in FIG. 3, a conventional silicon nitride etch is carried out, etching the Si 3 N 4 layer exposed by slots 15 , 16 and 17 . Thereafter, a trench etch is carried out, etching the oxide layer 12 exposed by slots 15 , 16 and 17 , and thereafter etching narrow trenches 20 , 21 and 22 . The trenches may have any desired depth, width and spacing which can be easily selected by those skilled in the art to produce the desired end device characteristics. However, trenches 21 and 22 and the other trenches in the active area are closer together than trench 21 and termination trench 20 .

A boron implant (1E14/cm 2 ) is next carried out to implant boron regions 23 , 24 and 25 at the bottoms of trenches 20 , 21 and 22 respectively as shown in figure 3 .

Thereafter, and as shown in FIG. 4, the resist 14 is stripped and the boron implants are driven at a suitable temperature, for a suitable time, to form P diffusions 26 , 27 and 28 which from P/N junctions to the N − silicon 10 .

As next shown in FIG. 5, a wet oxide etch is carried out etch the oxide 12 beneath the nitride layer 13 . The spacing between the trenches 21 and 22 in the active area are sufficiently close that the wet etch completely etches all oxide 13 from under nitride 12 . However, the trenches 21 and 20 are spaced sufficiently that the oxide etch is incomplete, learning oxide “islands” 12 a in FIGS. 5 and 6. The nitride 13 over the active area in FIG. 5 is unsupported and lifts away, but the nitride 13 over the termination area remains supported by oxide islands 12 a.

Thereafter, and as shown in FIG. 6 a metal deposition (aluminum) is carried out, forming metal contact 30 over the active area and filling trenches 20 , 21 and 22 . The contact of metal 30 to silicon surfaces 40 to 44 in FIG. 6 produces a very large area Schottky contact, while the metal in trenches 21 and 22 contact P regions 26 , 27 and 28 .

Thereafter, the back surface of wafer 10 is ground back to a desired thickness, and a back metal is deposited on the back surface. A conventional forming gas anneal is then carried out to complete the process.

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.