Mixing digital to analog converter

This invention relates to a mixing digital to analog converter (DAC) and more particularly to such a mixing DAC which operates internally, without the need for an extra mixer circuit.

Conventional digital to analog converters (DAC's) receive a digital input at a predetermined rate and provide an analog output at the same rate. In RF applications the output of the DAC is then up-converted through a separate mixer circuit. Additionally, high frequency DACs suffer from clock jitter which causes errors in the analog output signal. Jitter is caused by dynamic errors at the switching instant. One approach to the jitter problem, the return to zero approach, reduces the jitter by reducing the current to zero at the instant of switching.

This invention provides a mixing DAC for up-converting the analog output from the digital input without additional mixer circuits.

It is a further object of this invention to provide such a mixing DAC which preserves the return to zero solution to the jitter problem.

The invention results from the realization that a mixing DAC which automatically, internally, up-converts the analog output from the digital input can be achieved by varying the current output from each current source and each DAC. The current output has a plurality of peaks occurring at a predetermined rate, each clock period resulting in an analog output from the DAC which is up-converted to a rate commensurate to the predetermined input rate.

This invention features a mixing DAC including an analog output network, a current source, and a current switching circuit connected between the current source and the analog output network. A switch driver circuit responsive to a digital input at a first rate and a clock signal having a predetermined period, drives the current switching circuit to selectively interconnect the current source and the analog output network. A waveform generator drives the current source to produce an output current including a plurality of peaks at a second rate during each clock period to up-convert the response energy of the DAC analog output to approximately the second rate.

In a preferred embodiment, the current source, the current switching circuit, and the switch driver circuit may constitute a cell and there may be a plurality of such cells in the DAC. One waveform generator may drive all of the cells or there may be a waveform generator included in each cell. The current source in each cell may produce the output current at the same second rate. At least some of the current sources may produce the output current at other than the second rate. A current generator output current may be substantially sinusoidal. There may be valleys between the peaks of the current source output current and the valleys may be at substantially zero current.

Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:

FIG. 1 is a simplified schematic block diagram of a mixing digital to analog converter according to this invention;

FIG. 2 illustrates the current in each element and total output current occurring in the DAC of FIG. 1; and

FIG. 3 is a power spectrum of the DAC response plotted against frequency for prior art DAC's and the mixing DAC according to this invention.

There is shown in FIG. 1 a mixing digital to analog converter 10 according to this invention including one or more cells 12 , 12 1 , 12 2 , 12 n each of which as illustrated by cell 12 includes a current switching circuit 14 , a switch driver 16 which drives current switch 14 . Current switch 14 connects current source 18 to analog output network 20 . Switch driver 16 responds to the data input on line 22 and the clock input on line 24 to apply the clocked data to current switch 14 and selectively apply the current source to analog output network 20 .

In accordance with this invention, control waveform generator 26 drives current source 18 so that instead of a constant current it provides a varying current 30 , FIG. 2, having a plurality of peaks, that is at least two peaks for each clock cycle. The clock cycle, in FIG. 2, is defined as T. The current I 1 is provided by source 18 in FIG. 1 . The frequency of the output current, then, of current source 18 as controlled by waveform generator 26 , has a frequency equal to n times the clock frequency. As a result, the output current I total appearing on analog output network 20 appears as at 32 , FIG. 2, where the switching envelope 34 follows the clocked data, but the underlying output signal 32 has approximately the frequency of the current source fluctuation as controlled by waveform generator 26 . Thus, the frequency response energy of the DAC analog output has been up-converted to the vicinity of the frequency of the control signal from waveform generator 26 and appears on the analog output network 20 . By making the frequency f control of the waveform generator output to current source 18 equal to n times the clock signal, the valleys or zero points 36 and 38 , FIG. 2, are made to align with the transitions so that the clock jitter benefits of a typical return to zero circuit can be maintained. In one embodiment these are zeroed, but this is not a necessary limitation of the invention. In addition, although the waveforms are shown as sinusoids in FIG. 2, this is not a necessary limitation of the invention. Any periodic peak configuration will work.

The effectiveness of the invention is illustrated in FIG. 3 where a conventional DAC power spectrum 50 , FIG. 3, which is a function of sine x/x have nulls at f clock , 2f clock , 3f clock and so on. Thus, using a high frequency image at the output is contraindicated because of the low energy nulls at each of the clock multiples. In accordance with this invention as shown by characteristic 52 , the power curve can be controlled so that instead of a null at, for example 2f clock , there can be a peak and thus the DAC up conversion can be effected efficiently by simply changing the value of n. The lobe 54 of characteristic 52 can be reshaped so that the peak point 56 now over 2f clock can be positioned over 3f clock , 4f clock and so on. Although in FIG. 1 control waveform generator 26 is shown as supplying the same control 60 to each current source 18 , 18 1 , etc. this is not a necessary limitation of the invention. For example, waveform generator 26 could provide a different control signal to each of current sources 18 , 18 1 , etc. one over line 60 to current source 18 , another over line 62 to current source 18 1 , another over line 64 to current source 18 2 , and so on. Alternatively, instead of a universal waveform generator 26 , there can be a separate waveform generator 26 ′, 26 ′ 1 , 26 ′ 2 associated with each current source which may provide the same or differing control to its respective current source.

Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.