Semiconductor memory device internal voltage generator and internal voltage generating method

1. Field of the Invention

The present invention relates to a semiconductor memory device, and more particularly, to an internal voltage generator of a semiconductor memory device and an internal voltage generating method thereof.

2. Description of the Related Art

In most cases, semiconductor memory devices include internal voltage generators. An internal voltage generator receives an external voltage externally applied thereto and generates an internal voltage having a level lower than the external voltage. The internal voltage generated in the internal generator is used as the power voltage of a memory cell array in order to reduce power consumption, obtain high noise immunity, and insure stable operational properties.

FIG. 1 is a circuit diagram of a conventional internal voltage generator. Referring to FIG. 1, the conventional internal voltage generator includes a PMOS driving transistor P 11 , a comparator 11 , an OR gate 13 , a PMOS transistor P 12 , and NMOS transistors N 11 and N 12 .

The OR gate 13 receives input signals VCCAP 1 and VCCAP 2 and generates a predetermined control signal VCCAE, which is a pulse type signal. The input signals VCCAP 1 and VCCAP 2 of the OR gate 13 are pulse signals that are generated in response to a signal activated during an active period of a semiconductor memory device.

If the NMOS transistor N 11 is turned on when the predetermined control signal VCCAE is logic “high”, the comparator 11 becomes active. When the input signal VCCAP 2 of the OR gate 13 is logic “low”, the comparator 11 compares an internal voltage VCCA fed back to the comparator 11 via the PMOS transistor P 12 with a predetermined reference voltage VREF and generates a driving signal DR depending on the results. When the input signal VCCAP 2 of the OR gate 13 is logic “high”, the comparator 11 compares a voltage input via the NMOS transistor N 12 with the reference voltage VREF and generates the driving signal DR depending on the results.

An external voltage VDD is applied to the source of the PMOS driving transistor P 11 , and the driving signal DR is applied to the gate of the PMOS driving transistor P 11 . The internal voltage VCCA is output from the drain of the PMOS driving transistor P 11 .

The conventional internal voltage generator shown in FIG. 1 is considerably affected, however, by variations in the external voltage VDD. For example, if the external voltage VDD increases, the gate-to-source voltage of PMOS driving transistor P 11 increases, causing P 11 to supply an excessive amount of electric charge. As a result, power consumption increases and the internal voltage VCCA becomes unstable.

To solve the above problems, it is a first object of the present invention to provide an internal voltage generator, for a semiconductor memory device, that can uniformly supply a predetermined amount of electric charge and can generate a stable internal voltage.

It is a second object of the present invention to provide an internal voltage generating method, for a semiconductor memory device, that can uniformly supply a predetermined amount of electric charge and can generate a stable internal voltage.

Accordingly, to achieve the first object, there is provided an internal voltage generator according to the present invention including: a PMOS driving transistor having a source to which the external voltage is applied, a gate to which a driving signal is applied, and a drain from which the internal voltage is output; and a driving signal generator that generates the driving signal. Here, the driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level during variations in the external voltage.

The internal voltage generator according to the present invention may further include a pull-up device that is connected to the gate of the PMOS driving transistor and pulls up the gate of the PMOS driving transistor.

According to a preferred embodiment of the present invention, the driving signal generator includes: a voltage divider that divides the internal voltage in response to a buffered control signal so as to generate a control voltage that is substantially uniform; and an inverter that uses the external voltage as a power voltage, inverts the buffered control signal in response to the control voltage, and outputs the driving signal.

To achieve the second object, there is provided an internal voltage generating method for a semiconductor memory device that generates an internal voltage having a level lower than an external voltage, the method including: generating a control voltage that is substantially uniform by dividing the internal voltage in response to a control signal; generating a driving signal by inverting the control signal in response to the uniform control voltage using the external voltage as a power voltage; and generating the internal voltage in response to the driving signal using the external voltage as a source.

The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

FIG. 1 is a circuit diagram of a conventional internal voltage generator; and

FIG. 2 is a circuit diagram of an internal voltage generator according to an embodiment of the present invention.

The present invention will now be described more fully with reference to the accompanying drawings, in which a preferred embodiment of the invention are shown. The same reference numerals in different drawings represent the same element.

FIG. 2 is a circuit diagram of an internal voltage generator according to an embodiment of the present invention. Referring to FIG. 2, an internal voltage generator according to the embodiment of the present invention includes a PMOS driving transistor P 21 , a driving signal generator 21 , a pull-up device 23 , and a buffer 25 .

An external voltage VDD is applied to the source of the PMOS driving transistor P 21 , and a driving signal DR is applied to the gate of the PMOS driving transistor P 21 . An internal voltage VCCA is output from the drain of the PMOS driving transistor P 21 . In other words, the PMOS driving transistor P 21 , which is an internal voltage driver, receives the external voltage VDD in response to the driving signal DR and drives the internal voltage VCCA.

The buffer 25 buffers a predetermined control signal VCCAE and outputs a buffered control signal VCCAEB. The driving signal generator 21 generates the driving signal DR in response to the buffered control signal VCCAEB output from the buffer 25 . The predetermined control signal VCCAE is a pulse type signal that is generated in response to a signal activated during an active period of a semiconductor memory device.

The driving signal generator 21 maintains a stable voltage Vgs between the gate and source of the PMOS driving transistor P 21 , even with variations in the external voltage VDD. Specifically, the driving signal generator 21 includes a voltage divider 21 a and an inverter 21 b . The voltage divider 21 a divides the internal voltage VCCA in response to the buffered control signal VCCAEB and generates a control voltage VCNT that is substantially uniform. The inverter 21 b inverts the buffered control signal VCCAEB in response to the control voltage VCNT and outputs the driving signal DR. The inverter 21 b uses the external voltage VDD as a power voltage.

The voltage divider 21 a includes a PMOS transistor P 22 and NMOS transistors N 21 and N 22 . The internal voltage VCCA is applied to the source of the PMOS transistor P 22 . Ground voltage VSS is applied to the gate of the PMOS transistor P 22 . The control voltage VCNT is output from the drain of the PMOS transistor P 22 .

The drain of the NMOS transistor N 21 is connected to the drain of the PMOS transistor P 22 , and the buffered control signal VCCAEB is applied to the gate of the NMOS transistor N 21 . The drain and gate of the NMOS transistor N 22 are connected to the source of the NMOS transistor N 21 . The source of the NMOS transistor N 22 is connected to the ground voltage VSS.

The inverter 21 b includes a PMOS transistor P 23 and NMOS transistors N 23 and N 24 . The external voltage VDD is applied to the source of the PMOS transistor P 23 . The buffered control signal VCCAEB is applied to the gate of the PMOS transistor P 23 . The driving signal DR is output from the drain of the PMOS transistor P 23 .

The drain of the NMOS transistor N 23 is connected to the drain of the PMOS transistor P 23 . The buffered control signal VCCAEB is applied to the gate of the NMOS transistor N 23 . The drain of the NMOS transistor N 24 is connected to the source of the NMOS transistor N 23 . The control voltage VCNT is applied to the gate of the NMOS transistor N 24 . The ground voltage VSS is applied to the source of the NMOS transistor N 24 .

The voltage divider 21 a and the inverter 21 b can be embodied in many forms different from the structure described above.

The pull-up device 23 is connected to the gate of the PMOS driving transistor P 21 and pulls up the gate of the PMOS driving transistor P 21 . As illustrated in FIG. 2, the pull-up device 23 includes a PMOS transistor P 24 and an NMOS transistor N 25 . However, the structure of the pull-up device 23 may be varied.

The operation and internal voltage generating method of the internal voltage generator according to the present invention will now be described in detail.

When the buffered control signal VCCAEB becomes logic “high”, the NMOS transistor N 21 of the voltage divider 21 a is turned on. Then the internal voltage VCCA is divided by the PMOS transistor P 22 and NMOS transistors N 21 and N 22 of the voltage divider 21 a acting as resistors. The divided voltage, that is, the control voltage VCNT, is output from the drain of the PMOS transistor P 22 .

Since the internal voltage VCCA generally has a uniform voltage level, the control voltage VCNT also has a uniform voltage level. The control voltage VCNT has a voltage level sufficient to turn on the NMOS transistor N 24 of the inverter 21 b.

The inverter 21 b inverts the buffered control signal VCCAEB in response to the control voltage VCNT and outputs the driving signal DR. When the buffered control signal VCCAEB is logic “low”, the PMOS transistor P 23 of the inverter 21 b is turned on, and thus the gate of the PMOS driving transistor P 21 is pulled up to the external voltage level VDD. In other words, the driving signal DR becomes logic “high”. Accordingly, the PMOS driving transistor P 21 is turned off, and the internal voltage VCCA is not generated.

When the buffered control signal VCCAEB is logic “high”, the NMOS transistor of the inverter 21 b is turned on, and thus current is pumped up from the gate of the PMOS driving transistor P 21 to the ground voltage VSS through the NMOS transistors N 23 and N 24 . At this time, the control voltage VCNT is almost uniform despite variations in the external voltage VDD, and thus the pump up current is uniformly maintained as well.

Therefore, if the external voltage VDD increases, the gate voltage of the PMOS driving transistor P 21 also increases by the same potential difference as the external voltage VDD. If the external voltage VDD decreases, the gate voltage of the PMOS driving transistor P 21 also decreases by the same potential difference as the external voltage VDD. Accordingly, a voltage Vgs between the gate and source of the PMOS driving transistor P 21 is uniformly maintained with variations in the external voltage VDD. Thus, the PMOS driving transistor P 21 supplies a predetermined amount of electric charge with variations in the external voltage VDD and outputs an internal voltage VCCA that is stable.

As described above, the internal voltage generator of the present invention and the internal voltage generating method thereof can uniformly supply a predetermined amount of electric charge and generate a stable internal voltage.

While this invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.