Power cutoff device

The present invention relates to a power cutoff device, and more particularly to a power cutoff device capable of suitably adjusting transient characteristics of a power voltage caused at a cutoff of the power voltage being supplied to a load circuit.

The present application claims priority from Japanese Application No. 2001-072152, the disclosure of which is incorporated herein for all purpose.

It has been known that some types of integrated circuit devices, such as an LSI and a VLSI, hybrid circuit devices of an analog circuit and a digital circuit, multi-functional, high-performance electric circuit boards having thereon mounted many electronic circuits demand more than one power voltage in order to operate in a satisfactory manner.

Such integrated circuit devices, hybrid circuit devices, and electric circuit boards (hereinafter, referred to collectively as the electronic circuit device) are generally arranged in such a manner that, as shown in FIG. 6, power input terminals P 1 , P 2 , and P 3 , and a ground terminal PGND provided to an electronic circuit device DVC are connected to a multi-power circuit VREG with a common ground GND, whereby a plurality of constant voltages V 1 , V 2 , and V 3 generated at the multi-power circuit VREG are applied as power voltages Vcc 1 , Vcc 2 , and Vcc 3 , respectively.

FIG. 6 is a view showing a case where the electronic circuit device DVC is provided with three electronic circuits (hereinafter, referred to as the load circuits) LOAD 1 , LOAD 2 , and LOAD 3 respectively operating on three power voltages each having a different value, and constant voltages V 1 , V 2 , and V 3 generated at the multi-power circuit VREG are applied to the load circuits LOAD 1 , LOAD 2 , and LOAD 3 through open/close switches SW 1 , SW 2 , and SW 3 , respectively.

Herein, by setting a control signal Son/off, which is outputted from an ON/OFF control circuit CNT for controlling power-up and power cutoff, to the logical level “H”, the open/close switches SW 1 , SW 2 , and SW 3 are simultaneously closed (switched ON), whereupon the constant voltages V 1 , V 2 , and V 3 are applied to the load circuits LOAD 1 , LOAD 2 , and LOAD 3 , respectively. On the other hand, by shifting the control signal Son/off to the logical level “L” from “H”, the closed open/close switches SW 1 , SW 2 , and SW 3 are simultaneously opened (switched OFF), whereupon the constant voltages V 1 , V 2 , and V 3 respectively being applied to the LOAD 1 , LOAD 2 , and LOAD 3 are cut off.

According to the typical arrangement of connecting the multi-power circuit VREG to the electronic circuit device DVC as shown in FIG. 6, however, in a case where the control signal Son/off is shifted to the logical level “L” from “H”, and the constant voltages V 1 , V 2 , and V 3 respectively being applied to the load circuits LOAD 1 , LOAD 2 , and LOAD 3 are cut off by opening the open/close switches SW 1 , SW 2 , and SW 3 at this point of change (hereinafter, referred to as the cutoff point) toff, as shown in FIG. 7 by way of example, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 start to attenuate to the ground level as residual voltages in their respective load circuits LOAD 1 , LOAD 2 , and LOAD 3 while exhibiting different transient characteristics.

In other words, time constants related to the power voltages Vcc 1 , Vcc 2 , and Vcc 3 may vary from each other depending on a difference in the standards among the load circuits LOAD 1 , LOAD 2 , and LOAD 3 , a difference in wiring capacitances and resistance values between the multi-power circuit VREG and each of the load circuits LOAD 1 , LOAD 2 , and LOAD 3 . Thus, even when the power is cut off simultaneously at the cutoff point toff, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 actually have different transient characteristics in the transient period after the cutoff point toff, and therefore, a time necessary to reach the ground level, an attenuation factor, etc. may vary for each.

Accordingly, voltages determined in advance by the ratings or the like which are not supposed to be applied, are applied to the load circuits LOAD 1 , LOAD 2 , and LOAD 3 during the transient period since the cutoff point toff until the power voltages Vcc 1 , Vcc 2 , and Vcc 3 attenuate to the ground level, which poses a problem that the load circuits LOAD 1 , LOAD 2 , and LOAD 3 cause a malfunction, break, or shorten their service lives.

For example, suppose that the electronic circuit DVC may possibly cause a malfunction at the load circuits LOAD 1 , LOAD 2 , and LOAD 3 unless the power voltages Vcc 1 , Vcc 2 , and Vcc 3 respectively applied to the load circuits LOAD 1 , LOAD 2 , and LOAD 3 are set to satisfy an inequality, Vcc 1 >Vcc 2 >Vcc 3 during a normal operation, and during the transient period after the cutoff point toff, the power voltage Vcc 3 attenuates to the ground level first followed by the power voltage Vcc 1 , and the power voltage Vcc 2 attenuates gradually in comparison with the power voltage Vcc 1 . Then, as shown in FIG. 7, there is a problem that the power voltages Vcc 1 , Vcc 2 , and Vcc 3 do not attenuate in accordance with the predetermined order and with predetermined voltage values because of influences of the time constants or the like.

The present invention has been devised to solve the conventional problems, and therefore, has an object to provide a power cutoff device capable of suitably adjusting the transient characteristics of a power voltage caused at a cutoff of the power voltage being supplied to a load circuit or the like, for example, a power cutoff device for allowing suitable use of various kinds of electronic circuit devices operating on more than one power voltage.

In order to achieve the above and other objects, a power cutoff device of the present invention is a power cutoff device for cutting off a power voltage being supplied to a load circuit, including: power voltage detecting means and current sink means provided between a power line and a ground line, the power line supplying a voltage generated by power means to the load circuit as the power voltage, wherein the power voltage detecting means detects a change in the power voltage generated on the power line and outputs a detection signal; and the current sink means sets a sink current corresponding to a level of the detection signal and sinks a current from the power line toward the ground line.

According to the power cutoff device arranged as above, a supply of the power voltage from the power means to the load circuit is cut off, whereupon the power voltage enters the transient state. Then, the power voltage detecting means detects a power voltage in the transient state and outputs a detection signal. The current sink means sets a sink current corresponding to the level of the detection signal, and sinks a current from the power line toward the ground line according to the sink current.

By sinking the current according to the sink current, it is possible to suitably adjust the attenuation factor of the power voltage in the transient state, a time necessary to reach the level of the ground line, etc.

Also, a power cutoff device of the present invention is a power cutoff device for cutting off a plurality of power voltages being supplied to a plurality of load circuits, including: power voltage detecting means and current sink means provided between a plurality of power lines and a ground line, the plurality of power lines supplying a plurality of voltages generated by power means to the plurality of load circuits as the plurality of power voltages, wherein the power voltage detecting means detects a change in a power voltage generated on any of the plurality of power lines and outputs a detection signal, and the current sink means sets a sink current corresponding to a level of the detection signal and sinks a current from each of the plurality of power lines toward the ground line independently.

Further, a power cutoff device of the present invention is a power cutoff device for cutting off a plurality of power voltages being supplied to a plurality of load circuits, including: power voltage detecting means and current sink means provided between a plurality of power lines and a ground line, the plurality of power lines supplying a plurality of voltages generated by power means to the plurality of load circuits as the plurality of power voltages, wherein the power voltage detecting means detects a change in a power voltage generated on each of the plurality of power lines and outputs a detection signal corresponding to each power voltage, and the current sink means sets a sink current corresponding to a level of the detection signal corresponding to each power voltage and sinks a current from each of the plurality of power lines toward the ground line independently.

According to the power cutoff devices arranged as above, when a supply of each power voltage to an electronic circuit device provided with a plurality of load circuits each operating independently on their respective power voltages is cut off, the power voltage detecting means detects at least one of power voltages in the transient state and outputs a detection signal. The current sink means sets a sink current corresponding to the level of the detection signal, and sinks a current from each power line toward the ground line independently. Hence, it is possible to suitably adjust the attenuation factor of each power voltage being applied to their respective load circuits, a time necessary to reach the level of the ground line for each, etc. Consequently, in case that the transient characteristics of the power voltages with respect to each other are determined in advance by the ratings or the like to prevent the occurrence of a malfunction of the load circuits or the like, it is possible to adequately set transient characteristics by sinking a current from each power line to the ground line independently.

In addition, the power voltage detecting means and the current sink means operate upon supply of electricity from the power voltage generated on the power line.

According to the above arrangement, a special power or the like for operating the power cutoff device can be omitted, thereby making it possible to reduce the power consumption, and downsize and simplify the circuit.

Furthermore, the current sink means sets a sink current equivalent to a value of the detection signal outputted from the power voltage detecting means and amplified by an adjustable amplification factor.

According to the above arrangement, by adjusting the amplification factor, it is possible to adequately adjust a value of a sink current. Consequently, it is possible to accurately adjust a change in the power voltage in the transient state.

These and other objects and advantages of the present invention will become clear from the following description with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram depicting an arrangement of a power cutoff device according to one embodiment of the present invention;

FIG. 2 is a circuit diagram showing more concretely the arrangement of the power cutoff device according to one embodiment of the present invention;

FIG. 3 is a characteristic graph explaining an operation of the power cutoff device according to one embodiment of the present invention;

FIG. 4 is a characteristic graph explaining further the operation of the power cutoff device according to one embodiment of the present invention;

FIG. 5 is a block diagram depicting an arrangement of a modified example of the power cutoff device according to one embodiment of the present invention;

FIG. 6 is a block diagram depicting a conventional arrangement for supplying power voltages to an electronic circuit device which needs more than one power voltage; and

FIG. 7 is a graph showing an example of a change in the power voltages caused during a transient period after a power cutoff.

The following description will describe one embodiment of the present invention with reference to the accompanying drawings. FIG. 1 is a block diagram depicting an arrangement of a power cutoff device of the present embodiment, and FIG. 2 is a circuit diagram showing more concretely the arrangement of the power cutoff device of the present embodiment.

For ease of explanation, the following description will describe a case where a power cutoff device 4 of the present embodiment is applied to an electronic circuit device 2 which needs three power voltages, 5 volts, 3.3 volts, and 2.7 volts, as an example of the electronic circuit device which needs more than one power voltage, such as an integrated circuit device, a hybrid circuit device, and an electric circuit board.

Referring to FIG. 1, three voltage regulators A 1 , A 2 , and A 3 are connected to a large-capacity main power I for generating and outputting a predetermined voltage Vi from electricity obtained from an alternating commercial power or a car battery, and the voltage regulators A 1 , A 2 , and A 3 are designed so that they output constant voltages V 1 (=5 volts), V 2 (=3.3 volts), and V 3 (=2.7 volts), respectively.

A multi-power circuit VREG as power means is composed of the three voltage regulators A 1 , A 2 , and A 3 or the three voltage regulators Al, A 2 , and A 3 plus the main power 1 .

Herein, the grounds of the voltage regulators A 1 , A 2 , and A 3 are connected respectively to ground lines GL 1 , GL 2 , and GL 3 , which are commonly connected to a ground GND of the main power 1 .

Voltage output terminals (no numerical references are given) of the voltage regulators A 1 , A 2 , and A 3 are connected to open/close switch elements B 1 , B 2 , and B 3 , respectively, each of which is composed of a switching power transistor or the like having a high withstand voltage and a bulk power, and the opening and closing operations of the open/close switch elements B 1 , B 2 , and B 3 are controlled simultaneously by a control signal Son/off outputted from a control circuit 3 .

When the control signal Son/off is set to the logical level “H”, the open/close switch elements B 1 , B 2 , and B 3 are closed (switched ON) simultaneously, and when the control signal Son/off is shifted to the logical level “L” from “H”, the switching-ON open/close switch elements B 1 , B 2 , and B 3 are opened (switched OFF) simultaneously in synchronization with the point (cutoff point) toff at which the logical level has changed.

Power lines FL 1 , FL 2 , and FL 3 , which supply the electronic circuit device 2 with constant voltages V 1 , V 2 , and V 3 respectively as power voltages Vcc 1 , and Vcc 2 , and Vcc 3 , are connected to the output ends of the open/close elements B 1 , B 2 , and B 3 , respectively. As shown in the drawing, large-capacity capacitors (hereinafter, referred to as capacitance elements) C 1 , C 2 , and C 3 are connected across the power lines FL 1 , FL 2 , and FL 3 and the ground lines GL 1 , GL 2 , and GL 3 , respectively, so that the capacitance elements C 1 , C 2 , and C 3 stabilize the power voltages Vcc 1 , Vcc 2 , and Vcc 3 , respectively.

Then, as shown in the drawing, the electronic circuit device 2 provided with a load circuit CQT 1 operating on the power voltage Vcc 1 (=5.0 volts), a load circuit CQT 2 operating on the power voltage Vcc 2 (=3.3 volts), and a load circuit CQT 3 operating on the power voltage Vcc 3 (=2.7 volts) is connected to the power lines FL 1 , FL 2 , and FL 3 and to the ground lines GL 1 , GL 2 , and GL 3 as needed.

The power cutoff device 4 is connected across the power lines FL 1 , FL 2 , and FL 3 and the ground lines GL 1 , and GL 2 , and GL 3 .

To be more specific, the power cutoff device 4 is provided with an error detection unit DT and three variable current sink units E 1 , E 2 , and E 3 , and the error detection unit DT is connected across the power line FL 1 and the ground line GL 1 , the variable current sink units E 1 , E 2 , and E 3 are connected across the power line FL 1 and the ground line GL 1 , across the power line FL 2 and the ground line GL 2 , and across the power line FL 3 and the ground line GL 3 , respectively.

Further, when the control signal Son/off supplied from the control unit 3 shifts to the logical level “L” from “H”, the error detection unit DT detects a change in the power voltage Vcc 1 between the power line FL 1 and the ground line GL 1 from the point (cutoff point) toff at which the logical level has changed. To be more specific, when the control signal Son/off shifts to the logical level “L” from “H”, the open/close switch elements B 1 , B 2 , and B 3 are opened simultaneously as discussed above, whereby the supply of the power voltages to the electronic circuit device 2 is cut off. As a result, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 between the power lines FL 1 , FL 2 , and FL 3 and the ground lines GL 1 , GL 2 , and GL 3 , respectively, start to attenuate gradually to the ground level during the transient period after the cutoff point toff. The error detection unit DT detects a change in the power voltage Vcc 1 during the transient period, and outputs an error detection signal Sc which represents the detection result.

The variable current sink units E 1 , E 2 , and E 3 are provided with active elements, such as transistors, for respectively setting sink currents Is 1 , Is 2 , and Is 3 , which are proportional to the level of the error detection signal Sc.

To be more specific, the variable current sink unit E 1 sets the sink current Is 1 equivalent to a value of the level of the error detection signal Sc amplified by a predetermined proportion coefficient k1, the variable current sink unit E 2 sets the sink current Is 2 equivalent to a value of the level of the error detection signal Sc amplified by a predetermined proportion coefficient k2, and the variable current sink unit E 3 sets the sink current Is 3 equivalent to a value of the level of the error detection signal Sc amplified by a predetermined proportion coefficient k3. Herein, the proportion coefficients k1, k2 and k3 can be adjusted to arbitrary values, which in turn makes it possible to set the sink currents Is 1 , Is 2 , and Is 3 independently.

Then, the variable current sink unit E 1 sinks the sink current Is 1 from the power line FL 1 toward the ground line GL 1 , the variable current sink unit E 2 sinks the sink current Is 2 from the power line FL 2 toward the ground line GL 2 , and the variable current sink unit E 3 sinks the sink current Is 3 from the power line FL 3 toward the ground line GL 3 .

Next, the following description will describe more concretely the arrangement of the power cutoff device 4 with reference to FIG. 2 . In FIG. 2, like components are labeled with like reference numerals with respect to FIG. 1 for ease of explanation.

The error detection unit DT is provided with an NPN transistor Q 1 and PNP transistors Q 2 and Q 3 . The base of the NPN transistor Q 1 is supplied with the control signal Son/off outputted from the control unit 3 through a buffer amplifier AMP and a resistor R 1 . Also, a bias resistor R 2 is connected across the base of the NPN transistor Q 1 and the emitter thereof connected to the ground line GL 1 , and the collector of the NPN transistor Q 1 is connected to the power line FL 1 through resistors R 4 and R 3 .

In regard to the PNP transistor Q 2 , the base is connected to a contact between the resistors R 3 and R 4 , and the emitter is connected to the power line FL 1 , while the collector is connected to the base of the PNP transistor Q 3 and to the ground line GLI through a resistor R 5 .

In regard to the PNP transistor Q 3 , as has been discussed above, the base is connected to the collector of the PNP transistor Q 2 and to the resistor R 5 , and the emitter is connected to the power line FL 1 , while the collector is connected to the ground line GL 1 through a resistor R 6 and to each of the bases of NPN transistors Q 4 , Q 5 , and Q 6 respectively included in the variable current sink units E 1 , E 2 , and E 3 .

According to the error detection unit DT arranged as above, when the control signal Son/off from the control circuit 3 shifts to the logical level “H”, the open/close switch elements B 1 , B 2 , and B 3 are closed (switched ON), whereupon the power line FL 1 is supplied with the constant voltage V 1 from the voltage regulator A 1 as the power voltage Vcc 1 , and further, the NPN transistor Q 1 is turned ON.

Then, a predetermined current from the power line FL 1 flows into the turning-ON NPN transistor Q 1 through the resistors R 3 and R 4 , and a predetermined voltage drop occurs at the resistor R 3 , which turns ON the PNP transistor Q 2 also as it is forward-biased.

Further, a predetermined current flows in the resistor R 5 from the power line FL 1 through the PNP transistor Q 2 , and a predetermined voltage drop occurs at the resistor R 5 , which turns OFF the PNP transistor Q 3 , whereby the error detection signal Sc generated across the resistor R 6 and the ground line GL 1 are at substantially the same potential. Hereinafter, the potential at which the error detection signal Sc and the ground line GL 1 will be at substantially the same potential is referred to as the OFF potential.

On the other hand, when the control signal Son/off from the control unit 3 shifts to the logical level “L” from “H”, the open/close switch elements B 1 , B 2 , and B 3 are opened (switched OFF) by the shifting to the logical level “L”, whereby the supply of the constant voltage V 1 from the voltage regulator A 1 to the power line FL 1 is cut off, and further, the NPN transistor Q 1 is turned OFF.

It should be appreciated, however, that because of the capacitance and resistance of the load circuit CQTI and the power line FL 1 and the influence of the capacitance element C 1 , the power voltage Vcc 1 of the power line FL 1 does not drop to exactly the same level as the ground line GL 1 at the point (cutoff point) toff at which the control signal Son/off has shifted to the logical level “L” to “H”, and instead, it enters the transient state.

Hence, while the power voltage Vcc 1 is in the transient state (that is, during the transient period), the NPN transistor Q 1 stays OFF and so does the PNP transistor Q 2 as a consequence, and further, the PNP transistor Q 3 is set under a forward-biased condition by the resistor R 5 connected to the ground line GL 1 .

Hence, a current, which corresponds to a residual voltage when the power voltage Vcc 1 is in the transient state, flows toward the resistor R 6 from the voltage line FL 1 through the PNP transistor Q 3 , whereby the error detection signal Sc proportional to the residual voltage is generated across the resistor R 6 .

As has been discussed, the error detection unit DT outputs the error detection signal Sc which will be at the OFF potential when the control signal Son/off is set to the logical level “H”, and when the control signal Son/off is set to the logical level “L”, it detects the power voltage Vcc 1 in the transient state and outputs the error detection signal Sc proportional to the power voltage Vcc 1 (residual voltage).

The variable current sink unit E 1 is composed of the NPN transistor Q 4 and a resistor R 7 , and in regard to the NPN transistor Q 4 , its collector is connected to the power line FL 1 , and as has been discussed above, its base is connected to the collector of the PNP transistor Q 3 , while its emitter is connected to the ground line GL 1 through the resistor R 7 . In other words, the NPN transistor Q 4 establishes a common-emitter connection somewhere between the power line FL 1 and the ground line GL 1 together with the resistor (so-called emitter resistor) R 7 connected to the emitter.

Hence, the NPN transistor Q 4 stays OFF when it is supplied with the error detection signal Sc which will be at the OFF potential from the error detection unit DT, in other words, when the load circuit CQT 1 operates normally by virtue of the power voltage Vcc 1 (=5.0 volts).

Consequently, the sink current Is 1 becomes nearly 0, and the variable current sink unit E 1 has substantially no effect on the power line FL 1 and the ground line GL 1 . Also, power consumption of the variable current sink unit E 1 is reduced to an extremely low, negligible level.

In contrast, during the transient period as discussed above, upon supplying the error detection signal Sc proportional to the power voltage Vcc 1 from the error detection unit DT to the NPN transistor Q 4 , the NPN transistor Q 4 sets the sink current Is 1 equivalent to a value of the error detection signal Sc amplified by the amplification factor (proportion coefficient) k1 which is determined by the base resistance (R B ), the current amplification factor (h FE ), and the base-emitter voltage (V BE ) of the NPN transistor Q 4 and the resistor R 7 .

Further, because of the common-emitter connection, the NPN transistor Q 4 has high output impedance at the power line FL 1 side (the impedance is high when the collector of the NPN transistor Q 4 is viewed from the power line FL 1 side), and for this reason, the sink current Is 1 proportional to the level of the error detection signal Sc is sunk from the power line FL 1 toward the ground line GL 1 without any influence of the impedance at the power line FL 1 side including the load circuit CQT 1 .

The variable current sink unit E 2 is composed of the NPN transistor Q 5 and a resistor R 8 , and in regard to the NPN transistor Q 5 , its collector is connected to the power line FL 2 , and as has been discussed above, its base is connected to the collector of the PNP transistor Q 3 , while its emitter is connected to the ground line GL 2 through the resistor R 8 , thereby establishing a common-emitter connection.

Hence, the NPN transistor Q 5 stays OFF when it is supplied with the error detection signal Sc which will be at the OFF potential from the error detection unit DT, in other words, when the load circuit CQT 2 operates normally by virtue of the power voltage Vcc 2 (=3.3 volts). Consequently, the sink current Is 2 becomes nearly 0, and the variable current sink unit E 2 has substantially no effect on the power line FL 2 and the ground line GL 2 .

In contrast, during the transient period as discussed above, upon supply of the error detection signal Sc proportional to the power voltage Vcc 1 (residual voltage) from the error detection unit DT, the NPN transistor Q 5 sets the sink current Is 2 equivalent to a value of the error detection signal Sc amplified by the amplification factor (proportion coefficient) k2 which is determined by the base resistance (RB), the current amplification factor (hFE), and the base-emitter voltage (VBE) of the NPN transistor Q 5 and the resistor R 8 .

Further, because of the common-emitter connection, the NPN transistor Q 5 has high output impedance at the power line FL 2 side (the impedance is high when the collector of the NPN transistor Q 5 is viewed from the power line FL 2 side). For this reason, the sink current Is 2 proportional to the level of the error detection signal Sc is sunk from the power line FL 2 toward the ground line GL 2 without any influence of the impedance at the power line FL 2 side including the load circuit CQT 2 .

The variable current sink unit E 3 is composed of the NPN transistor Q 6 and a resistor R 9 , and in regard to the NPN transistor Q 6 , its collector is connected to the power line FL 3 , and as has been discussed above, its base is connected to the collector of the PNP transistor Q 3 , while its emitter is connected to the ground line GL 3 through the resistor R 9 .

In other words, the NPN transistor Q 6 also establishes a common-emitter connection somewhere between the power line FL 3 and the ground line GL 3 together with the resistor R 9 in the same manner as the NPN transistors Q 4 and Q 5 .

Hence, the NPN transistor Q 6 stays OFF when it is supplied with the error detection signal Sc which will be at the OFF potential from the error detection unit DT, in other words, when the load circuit CQT 3 operates normally by virtue of the power voltage Vcc 3 (=2.7 volts). Consequently, the sink current Is 3 becomes nearly 0, and the variable current sink unit E 3 has substantially no effect on the power line FL 3 and the ground line GL 3 .

In contrast, during the transient period as discussed above, upon supply of the error detection signal Sc proportional to the power voltage Vcc 1 from the error detection unit DT, the NPN transistor Q 6 sets the sink current Is 3 equivalent to a value of the error detection signal Sc amplified by the amplification factor (proportion coefficient) k3 which is determined by the base resistance (R B ), the current amplification factor (h FE ), and the base-emitter voltage (V BE ) of the NPN transistor Q 6 and the resistor R 9 .

Further, because of the common-emitter connection, the NPN transistor Q 6 has high output impedance at the power line FL 3 side (the impedance is high when the collector of the NPN transistor Q 6 is viewed from the power line FL 3 side). For this reason, the sink current Is 3 proportional to the level of the error detection signal Sc is sunk from the power line FL 3 toward the ground line GL 3 without any influence of the impedance at the power line FL 3 side including the load circuit CQT 3 .

By setting the values of the resistors R 7 , R 8 and R 9 respectively provided to the variable current sink units E 1 , E 2 , and E 3 as needed, it is possible to adjust the amplification factors (proportion coefficients) k1, k2, and k3 independently during the transient period, which in turn makes it possible to adjust the sink currents Is 1 , Is 2 , and Is 3 independently.

Next, the following description will describe an operation of the current cutoff circuit DT of the present embodiment with reference to FIGS. 3 and 4.

FIG. 3 is a characteristic graph obtained from experiments, and shows a change in the power voltages Vcc 1 , Vcc 2 , and Vcc 3 during the transient period when the open/close switch elements B 1 , B 2 , and B 3 are opened simultaneously at the cutoff point toff while the constant voltages V 1 (=5.0 volts), V 2 (=3.3 volts), and V 3 (=2.7 volts) generated respectively at the voltage regulators A 1 , A 2 , and A 3 are applied to the load circuits CQT 1 , CQT 2 , and CQT 3 as the power voltages Vcc 1 , and Vcc 2 , and Vcc 3 , respectively. FIG. 4 is a characteristic graph showing a change in the sink currents Is 1 , Is 2 , and Is 3 measured under the same conditions as those of FIG. 3 .

Design values of the transistors Q 1 through Q 6 , resistors R 1 through R 9 , capacitance elements C 1 through C 3 and the like set in obtaining the experimental results are the design factors which can be determined as needed, and such values are not specified herein for ease of explanation. Also, the description of the load circuits CQT 1 , CQT 2 , and CQT 3 as to their sizes and the like is omitted.

When the above-described control signal Son/off is set to the logical level “H” after desired values are set in the resistors R 7 , R 8 , and R 9 respectively in the variable current sink units E 1 , E 2 , and E 3 , as shown in FIG. 3, the predetermined constant voltages V 1 , V 2 , and V 3 generated respectively at the voltage regulators A 1 , A 2 , and A 3 are supplied to the load circuits CQT 1 , CQT 2 , and CQT 3 as the power voltages Vcc 1 , Vcc 2 , and Vcc 3 , respectively. At this point, as shown in FIG. 4, the sink currents Is 1 , Is 2 , and ls 3 are nearly 0 ampere, and therefore, the circuit cutoff device 4 is virtually absent.

By shifting the control signal Son/off to the logical level “L” from “H” abruptly at the cutoff point toff, the open/close switch elements B 1 , B 2 , and B 3 are opened simultaneously, whereupon the power voltages Vcc 1 , Vcc 2 , and Vcc 3 enter the transient state immediately after the cutoff point toff.

Initially, as shown in FIG. 4, the sink currents Is 1 , Is 2 , and Is 3 surge abruptly almost in synchronization with the cutoff point toff, then start to attenuate over time during the transient period, and eventually drop to nearly 0 ampere.

At this point, there is a correlation that the sink currents Is 1 , Is 2 , and Is 3 shown in FIG. 4 change in response to a change in the power voltages Vcc 1 , Vcc 2 , and Vcc 3 shown in FIG. 3 as the residual voltages, whereas the power voltages Vcc 1 , Vcc 2 , and Vcc 3 shown in FIG. 3 as the residual voltages change in response to a change in the sink currents Is 1 , Is 2 , and Is 3 shown in FIG. 4, and according to this correlation, both the sink currents Is 1 , Is 2 , and Is 3 and the power voltages Vcc 1 , Vcc 2 , and Vcc 3 start to attenuate.

Hence, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 do not attenuate naturally merely in accordance with the time constants under the influence of the peripheral capacitances, resistors, etc., but under the forced and regulated conditions according to the sink currents Is 1 , Is 2 , and Is 3 determined by the correlation discussed above.

Hence, by adjusting the resistors R 7 , R 8 , and R 9 , it is possible to allow the power voltages Vcc 1 , Vcc 2 , and Vcc 3 respectively applied to the load circuits CQT 1 , CQT 2 , and CQT 3 to attenuate in accordance with the predetermined order and with the predetermined voltage values in a programmable manner.

Incidentally, the characteristics view of FIG. 3 shows a case designed so that the power voltages Vcc 1 and Vcc 3 attenuate abruptly, and the power voltage Vcc 3 attenuates to 0 volt much sooner than the power voltage Vcc 1 , while the power voltage Vcc 2 attenuates gradually. It should be appreciated, however, that it is possible to change the attenuation characteristics of the power voltages Vcc 1 , Vcc 2 , and Vcc 3 in a programmable manner by adjusting the resistors R 7 , R 8 and R 9 .

Further, it should be noted that the error detection unit DT detects a change in the voltage V 1 on the power line FL 1 during the transient period, and outputs the error detection signal Sc as the detection result, whereupon the variable current sink units E 1 , E 2 , and E 3 set their respective sink currents Is 1 , Is 2 , and Is 3 with reference to a change in the level of the error detection signal Sc (in other words, a change in the power voltage Vcc 1 as the residual voltage). This means that the sink currents Is 2 and Is 3 are set relatively with reference to the sink current Is 1 . Hence, the power voltage Vcc 2 and Vcc 3 shown in FIG. 3 change with reference to a change in the power voltage Vcc 1 .

As has been discussed, the sink currents Is 2 and Is 3 or the power voltages Vcc 2 and Vcc 3 during the transient period are set with reference to the sink current Is 1 or the power voltage Vcc 1 . Hence, when the values of the resistors R 7 , R 8 , and R 9 are adjusted in advance, the resistor R 7 is adjusted first to measure the sink current Is 1 or the power voltage Vcc 1 , after which the resistors R 8 and R 9 are adjusted to adequate values with reference to the measurement result, so that the sink currents Is 2 and Is 3 or the power voltages Vcc 2 and Vcc 3 have the desired transient characteristics.

As has been discussed, it is possible to use the sink current Is 1 or the power voltage Vcc 1 as the reference in adjusting the rest of the sink currents Is 2 and Is 3 or the power voltages Vcc 2 and Vcc 3 by adjusting the resistors R 8 and R 9 . Hence, compared with a case where no reference is set, the adjustment operation becomes easier, which in turn makes it possible to improve the adjustment accuracy.

As has been discussed, according to the power cutoff device 4 of the present embodiment, the transient characteristics caused when the power voltages Vcc 1 , Vcc 2 , and Vcc 3 respectively being supplied to the load circuits CQT 1 , CQT 2 , and CQT 3 are cut off, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 can be changed forcedly according to the sink currents Is 1 , Is 2 , and Is 3 , respectively, even under the influences of the time constants generated depending on the circumstances, such as the load circuits CQT 1 , CQT 2 , and CQT 3 . Hence, the power voltages Vcc 1 , Vcc 2 , and Vcc 3 can be cut off in an adequate sequence at the load circuits CQT 1 , CQT 2 , and CQT 3 , respectively, which in turn allows suitable use of various kinds of electronic circuit devices operating on more than one power voltage.

Further, the power cutoff device 4 operates on electricity supplied from the power lines FL 1 , FL 2 , and FL 3 which supply the power voltages Vcc 1 , Vcc 2 , and Vcc 3 to the load circuits CQT 1 , CQT 2 , and CQT 3 , respectively. This makes it possible to omit a special power circuit for operating the power cutoff device 4 . Consequently, there can be offered an advantage that a simple, compact, less-power-consuming circuit arrangement can be achieved.

According to the power cutoff device 4 shown in FIGS. 1 and 2, the error detection unit DT is provided somewhere between the power line FL 1 and the ground line GL 1 to detect a change in the power voltage Vcc 1 on the power line FL 1 . It should be appreciated, however, that the error detection unit DT may be provided somewhere between the power line FL 2 and the ground line GL 2 to detect a change in the power voltage Vcc 2 on the power line FL 2 , so that the bases of the NPN transistors Q 4 , Q 5 , and Q 6 respectively in the variable current sink units E 1 , E 2 , and E 3 are driven based on an error signal Sc obtained by the detection.

Alternatively, the error detection unit DT may be provided somewhere between the power line FL 3 and the ground line GL 3 to detect a change in the power voltage Vcc 3 on the power line FL 3 , so that the bases of the NPN transistors Q 4 , Q 5 , and Q 6 respectively in the variable current sink units E 1 , E 2 , and E 3 are driven based on an error signal Sc obtained by the detection.

Further, as a modified example of the power cutoff device 4 of the present embodiment, the circuit may be arranged as shown in FIG. 5 . In FIG. 5, like components are labeled with like reference numerals with respect to FIG. 1 .

To be more specific, the power cutoff device 4 of FIG. 5 is provided with three error detection units DT 1 , DT 2 , and DT 3 , which are identical with the error detection unit DT shown in FIGS. 1 and 2, and provided between the power lines FL 1 , FL 2 , and FL 3 and the ground lines GL 1 , GL 2 , and GL 3 , respectively. The error detection unit DT 1 detects a change in the power voltage Vcc 1 on the power line FL 1 , the error detection unit DT 2 detects a change in the power voltage Vcc 2 on the power line FL 2 , and the error detection unit DT 3 detects a change in the power voltage Vcc 3 on the power line FL 3 .

The base of the NPN transistor Q 4 in the variable current sink unit E 1 is driven by an error detection signal Sc 1 outputted from the error detection unit DT 1 , the base of the NPN transistor Q 5 in the variable current sink unit E 2 is driven by an error detection signal Sc 2 outputted from the error detection unit DT 2 , and the base of the NPN transistor Q 6 in the variable current sink unit E 3 is driven by an error detection signal Sc 3 outputted from the error detection unit DT 3 .

According to the above arrangement, by adjusting the resistors R 7 , R 8 , and R 9 , it is possible to set the sink currents Is 1 , Is 2 , and Is 3 respectively set in the variable current sink units E 1 , E 2 , and E 3 independently in an almost complete manner. Hence, it is possible to adjust the transient characteristics of the power voltages Vcc 1 , Vcc 2 , and Vcc 3 independently and accurately for each of the load circuits CQT 1 , CQT 2 , and CQT 3 .

Also, the resistors R 7 , R 8 , and R 9 shown in FIG. 2 are fixed resistors. However, they may be replaced with variable resistors to facilitate the adjustment.

The error detection unit DT and the variable current sink units E 1 , E 2 , and E 3 shown in FIG. 2 are composed of a fewer transistors and resistors in reducing the circuit size and the number of the elements, etc. However, they may be composed of other electronic components, such as operational amplifiers, as long as they function in the same manner.

The above embodiment described the power cutoff device 4 for adjusting the transient characteristics of the three power voltages Vcc 1 , Vcc 2 , and Vcc 3 . It should be appreciated, however, that the present invention is not limited to the foregoing, and the present invention can adjust the transient characteristics of any number of power voltages by including as many error detection units and variable current sink units as necessary.

As has been described above, according to the power cutoff device of the present invention, the power voltage detecting means detects a power voltage in the transient state caused at a cutoff of the power voltage being supplied to the load circuit. Then, the current sink means sets a sink current corresponding to the level of a detection signal representing the detection result, and sinks a current from the power line to the ground line according to the sink current. Consequently, it is possible to suitably adjust an attenuation factor of the power voltage in the transient state, a time necessary to reach the level of the ground line, etc.

Also, in case that each power voltage is cut off for an electronic circuit device provided with a plurality of load circuits each operating independently on their respective power voltages, the power voltage detecting means detects at least one of power voltages in the transient state and outputs a detection signal. Then, the current sink means sets a sink current corresponding to the level of the detection signal, and sinks a current from each power line to the ground line independently. Hence, it is possible to suitably adjust the attenuation factor of each power voltage being applied to their respective load circuits, a time necessary to reach the level of the ground line for each, etc. Consequently, in case that the transient characteristics of the power voltages with respect to each other are determined in advance by the ratings or the like to prevent the occurrence of a malfunction of the load circuits or the like, it is possible to adequately set transient characteristics by sinking a current from each power line to the ground line independently, which in turn makes it possible to adapt the power cutoff device to various kinds of electronic circuit devices which need more than one power voltage.

In addition, the power voltage detecting means and the current sink means are arranged to operate upon supply of electricity from the power voltage generated on the power line. Consequently, a special power or the like for operating the power cutoff device can be omitted, thereby making it possible to reduce the power consumption, and downsize and simplify the circuit.

Furthermore, the current sink means is arranged to set a sink current equivalent to a value of the detection signal outputted from the power voltage detecting means and amplified by an adjustable amplification factor. Consequently, by adjusting the amplification factor, it is possible to adequately adjust a value of the sink current, thereby making it possible to accurately adjust a change in the power voltage in the transient state.

While there has been described what are at present considered to be preferred embodiments of the present invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover all such modifications as fall within the true spirit and scope of the invention.