DC/DC ZVS full bridge converter power supply method and apparatus

The present invention relates in general to power converters and, more specifically, to a full bridge DC/DC converter having an improved ZVS (Zero Voltage Switching) operation mode and primary winding clamp circuit to minimize secondary reverse recovery current losses.

A common practice in the field of power conversion is to use switching power supplies to convert DC voltage of one level to an isolated DC voltage at a second level. A circuit topology that is well suited for this purpose is the full bridge converter. One of the major disadvantages to switching power conversion is the losses associated with the switching elements in the power converter, and a common approach is to utilize nearly zero voltage switching (ZVS) to minimize these losses.

A common ZVS topology for a prior art full bridge converter is a phase-shifted full bridge. Such a circuit is described in detail in a Texas Instruments (formerly Unitrode Corp.) generated application note U-136A entitled “Phase Shifted Zero Voltage Transition Design Considerations and the UC3875 PWM Controller,” published in May 1997 and presently available from Texas Instruments, Inc. The phase shifted full bridge described therein relies on the parasitic elements of the switching elements, typically MOSFET transistors, and transformer primary winding inductance to transition the voltage across the switching elements to zero prior to turning on these switches. Since the switching losses are a function of the voltage across the switch prior to turn on, this approach reduces these losses to near zero under most operating conditions or characteristics.

While the phase-shifted full bridge minimizes switching losses associated with the primary circuit elements, it does not address inherent switching losses caused by output rectifier diode reverse recovery. These losses are primarily associated with the reverse recovery time of the secondary diodes, and result in ringing and emi (electromagnetic interference) when combined with parasitic elements of the main power transformer. Common prior art approaches to mitigate these losses have included using one or more of dissipative snubbers, saturable reactors, primary clamping circuits and low loss active filters.

By reducing the rate of change of current in the output rectifiers, the peak reverse recovery current is limited in some of the prior art circuits. Clamping elements on the primary side of the power train in other of those circuits have resulted in the capture of a majority of the reverse recovery energy in the primary resonant inductors, thus minimizing the dissipated energy.

Although these attempts to mitigate losses have, to various degrees, improved power dissipation efficiency from circuits not using the described approaches, there are still drawbacks of existing known circuits. These include, among others, cost, control, excessive emi and excessive switching losses.

It would thus be desirable to provide a converter with increased power conversion efficiency whereby a given size converter container can provide a larger amount of output power, or a given power rated converter can be packaged in a smaller container. It would also be desirable to provide a converter that minimizes component stresses and reduces generated high frequency interference signals, such as emi, for example.

The present invention comprises a full bridge non-resonant pulse-width-modulated (PWM) switching circuit. The circuit comprises four switches, inductive device(s), clamp diodes, a transformer and an output rectification stage including a filter connected to a transformer secondary. Capacitor and diode elements associated with the switching elements (part of the switching devices or external) are operatively connected to the four switches so as to switch current through the switches at substantially zero voltage (ZVS). The inductive device(s) and clamp diodes reduce the primary transition shoot through current resulting from reverse recovery of the transformer secondary rectification stage. The optional use of a current doubler as part of the filter circuit operates to reduce conduction losses in the main power transformer whereby even greater power conversion efficiency is obtained.

For a more complete understanding of the present invention, and its advantages, reference will now be made in the following Detailed Description to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a full bridge switching circuit DC/DC converter;

FIG. 2 illustrates an output rectification filter using half wave rectification and including current doubler inductances;

FIG. 3 illustrates an output rectification filter using half wave rectification and a center-tapped transformer secondary;

FIG. 4 illustrates an output rectification filter using full wave rectification and a non-center-tapped transformer secondary;

FIG. 5 is a complete switching cycle timing diagram of transistor and transformer voltage and current levels generated by the circuit shown in FIG. 1; and

FIG. 6 is a transition-timing diagram expansion of two selected transitions of the waveforms of FIG. 5 .

In the following description, various components will have dual designations of numbers and letters to simplify the association between voltage and current waveforms and the respective components.

In FIG. 1, a positive direct current power supply voltage terminal is designated as 10 while the negative terminal, which may be at ground, is designated as 12 . A pair of MOSFET (metal oxide on silicon field effect transistors) 14 (Q 1 ) and 16 (Q 2 ), hereinafter referred to simply as FETs for convenience, are shown connected in series between terminals 10 and 12 to form one leg (left hand) of a bridge converter. The drain “D” of FET 14 is connected to terminal 10 while the source “S” of FET 16 is connected to terminal 12 . A second pair of FETs 18 and 20 are also connected between terminals 10 and 12 in a like manner to form the other leg (right hand) of the bridge converter. Each of the referenced FETs is shown associated with a capacitance and a diode. MOSFETs inherently have a drain to source capacitance and a body diode effect in parallel therewith. Each of these diodes is designated with a “D” followed by the FET letter designator. As an example, the diode associated with FET 14 is labeled DQ 1 . On the other hand, where reference is made to the inherent capacitance of a capacitive element of switch Q 1 , it would be referred to as CQ 1 . While other switches, solid state or otherwise, may be used to practice the present invention, if they do not have sufficient inherent capacitance and similar diode characteristics, they may require such components external to the switching device, as these component characteristics are required to practice this invention. Each of the illustrated FETs include a switching signal input terminal or gate labeled “G”. As will be mentioned in detail later, a constant width square wave signal is applied to the gates of FETs Q 1 and Q 3 and is different from the PWM (pulse width modulated) signal applied to the gates of FETs Q 2 and Q 4 .

A terminal intermediate FETs 14 and 16 is labeled 22 . A similar terminal intermediate FETs 18 and 20 is labeled 24 . A pair of diodes 26 (D 1 ) and 28 (D 2 ) are connected in series between terminals 10 and 12 with the cathode of diode 26 connected to terminal 10 and the anode of diode 28 connected to terminal 12 . A common point or terminal between the diodes 26 and 28 is labeled 30 and further as “A”. An inductance 32 (also labeled L 1 ) is connected between terminals 22 and 30 . The diodes 26 and 28 , along with inductance 32 , form a first primary clamp circuit. A pair of diodes 34 and 36 , having an intermediate terminal 38 (further designated as “B”), are connected in a like fashion between terminals 10 and 12 . An inductance 40 (also labeled L 2 ) is connected between terminals 24 and 38 . The components 34 , 36 and 40 are shown in dash line format as the invention may be practiced by replacing these 3 components with a short between terminals 38 and 24 . A decision to use two primary clamp circuits rather than one may involve packaging considerations since two physically smaller inductors can provide the same performance as one large inductor. A primary winding 42 of a transformer 44 (also designated as “T 1 ”) is connected between terminals 30 and 38 . A secondary winding 46 of transformer 44 is connected to a secondary rectification and filter circuit block 48 .

FIG. 2 shows a transformer 60 (T 1 ) having a primary winding 62 and a secondary winding 64 . This transformer is equivalent to transformer 44 of FIG. 1. A pair of inductances 66 (L 1 S) and 68 (L 2 S) are shown connected in series across winding 64 . A common point 70 , between the inductances 66 and 68 , also serves as a negative voltage output terminal. A first rectifier diode 72 (CR 1 ) is connected between one end of winding 64 and a positive voltage output terminal 74 . A second rectifier diode 76 (CR 2 ) is connected between the other end of winding 64 and the positive voltage output terminal 74 . A filter capacitor 78 (Cout) is connected across filter output terminals 70 and 74 .

In FIG. 3, a transformer 90 is shown with a center tapped secondary winding 92 . This transformer 90 is operationally equivalent to transformer 44 of FIG. 1 in transferring signals to the block 48 . A first rectifier diode 94 (CR 1 ) is connected between one end of winding 92 and a junction point 96 . A second rectifier diode 98 (CR 2 ) is connected between the other end of winding 92 and the junction point 96 . A negative voltage filter output terminal 100 is connected to the center-tap of winding 92 . An inductance 102 is connected between junction point 96 and a positive voltage filter output terminal 104 . A filter capacitor 106 (Cout) is connected across filter output terminals 100 and 104 .

In FIG. 4, a transformer 110 (T 1 ) is shown having a secondary winding 112 . This transformer 110 is equivalent to transformer 44 of FIG. 1. A full bridge rectifier circuit 114 has its input terminals connected across winding 112 . One output terminal of circuit 114 is connected to a negative voltage filter output terminal 116 . An inductance 118 is connected between the other output terminal of circuit 114 and a positive voltage filter output terminal 120 . A filter capacitor 122 (Cout) is connected across filter output terminals 116 and 120 .

In FIG. 5, voltage and current waveforms 130 through 150 occurring over six periods of time are illustrated. Reference signal transition times T 0 through T 7 are designated with different length periods P 1 through P 6 shown between these stated reference times. Waveforms 130 , 132 , 134 , and 136 show, respectively, the voltage from gate to source of FETs Q 1 , Q 2 , Q 3 , and Q 4 . Waveforms 138 and 140 illustrate the voltage at junction points A ( 30 ) and B ( 38 ) in FIG. 1 . Waveforms 142 , 144 , 146 , and 148 illustrate the direction and amplitude of current flowing between the drain and source terminals of FETs Q 1 , Q 2 , Q 3 , and Q 4 , respectively. Waveform 150 illustrates the direction and amplitude of current flowing in the primary winding 42 of transformer 44 .

For further clarification, FIG. 6 expands the time scale to better illustrate the current and voltage alterations during signal transition times T 3 and T 4 . Although not specifically shown, similar, but inverted, actions would also take place during transition times T 6 and T 7 . In the description following, it should be noted that the times T 3 and T 6 can vary with respect to time T 0 , since these are indicative of the width of the pulse width modulated signal.

Referring now to FIG. 1, the circuit shown provides low or zero voltage switching (ZVS) and reduction of secondary rectification reverse recovery current. A DC voltage supply between terminals 10 and 12 of up to 400 V is typical for most applications. As expanded upon in FIGS. 2, 3 and 4 , the rectification and filter block 48 may comprise a current doubler and center-tapped or full wave bridge rectifier circuits. The output filter stage is typically a two-pole voltage filter formed by inductance(s) and capacitance.

Reference will now be made to FIGS. 1, 5 and 6 . It will be assumed for the purpose of this discussion that both primary clamp circuits (using L 1 and L 2 ) are connected as shown and a current doubler circuit, such as shown in FIG. 2, is being used in block 48 .

During time period P 1 , FETs Q 1 and Q 4 are conducting as shown by gate to source voltage waveforms 130 and 136 , as well as by current waveforms 142 and 148 . Diodes D 1 and D 4 are also conducting. At this same time, diodes D 2 and D 3 , as well as FETs 16 and 18 (Q 2 and Q 3 ), are non-conducting. Switches Q 1 and Q 4 are controlled to an ON state resulting in voltage waveform VA at junction point 30 being high and voltage VB at junction point 38 being low, as shown in waveforms 138 and 140 . The voltage supply is connected across the primary winding 42 of transformer T 1 and the secondary load currents, flowing in filter 48 , are reflected to primary winding 42 . Inductances L 1 and L 2 ( 32 and 40 ) are energized with reflected T 1 secondary winding rectifier reverse recovery current and load current. This results in diodes D 1 and D 4 ( 26 and 36 ) conducting the secondary rectifier reverse recovery current.

During the transition time T 2 , between periods P 1 and P 2 , diodes D 1 and D 4 switch to a non-conducting state, although FETs Q 1 and Q 4 remain conducting. During this transition time T 2 , diodes D 2 and D 3 , as well as FETs Q 2 and Q 3 are non-conducting. Diodes D 1 and D 4 switch to a non-conducting state as the reflected T 1 secondary winding load current increases to match the current of inductances 32 and 40 (L 1 and L 2 ).

During time period P 2 (between T 2 and T 3 ), diodes D 1 , D 2 , D 3 , and D 4 , as well as FETs Q 2 and Q 3 , remain non-conducting. Switches Q 1 and Q 4 remain controlled to an ON state, resulting in voltage waveform VA being high and voltage VB being low, as shown in waveforms 138 and 140 . The voltage supply is therefore connected across the primary 42 of transformer T 1 and the secondary load current is reflected to the T 1 primary winding 42 as well as to inductances 32 and 40 (L 1 and L 2 ).

During the transition time T 3 , between periods P 2 and P 3 , FET switch Q 4 is controlled to or turned to an OFF state resulting in the voltage at junction point 38 rising in amplitude, as shown in VB waveform 140 in both FIGS. 5 and 6. This rising voltage causes diode element DQ 3 , of FET 18 , to conduct current.

During time period P 3 , FET switch Q 1 remains controlled to an ON state, thus keeping the voltage at junction point 30 high, as shown in waveform 138 . Waveform VB remains high as secondary load currents reflected to the T 1 primary winding 42 maintain diode element DQ 3 , of FET Q 3 , in a conductive state. FETs Q 2 and Q 3 remain non-conducting as do diodes D 1 , D 2 , D 3 , and D 4 .

During the transition T 4 , between periods P 3 and P 4 , FET Q 1 is controlled to an OFF state, resulting in the voltage VA resonant transition to a low voltage state and causing diode element DQ 2 to conduct. FET switch Q 3 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 3 , of FET Q 3 . The voltage supply is therefore connected across the primary winding 42 of transformer T 1 . Further, during this transition time T 4 , the secondary rectifier reverse recovery and load currents are reflected to the T 1 primary winding as well as to inductances L 1 and L 2 ( 32 and 40 ).

During period P 4 , FET switch Q 2 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 2 . Voltage waveform VA remains low and voltage waveform VB remains high. The voltage supply is therefore connected across the primary winding 42 of transformer T 1 and the secondary winding load currents from block 48 are reflected to the T 1 primary winding 42 . Inductances L 1 and L 2 are energized with reflected T 1 secondary winding rectifier reverse recovery and load currents. This results in diodes D 2 and D 3 conducting the T 1 secondary rectifier reverse recovery current. As will be noted, during this time, diode elements DQ 2 and DQ 3 , as well as FETs Q 2 and Q 3 , are conducting, while diodes D 1 and D 4 , along with FETs Q 1 and Q 4 , are in a non-conducting state.

During transition time T 5 , between periods P 4 and P 5 , diodes D 2 and D 3 switch to a non-conducting state, as reflected T 1 secondary winding load current increases to match the current in inductances L 1 and L 2 . During transition time T 5 , FETs Q 2 and Q 3 remain conducting, while diodes D 1 and D 4 , as well as FETs Q 1 and Q 4 , remain non-conducting.

During time period P 5 , FET switches Q 2 and Q 3 remain controlled to an ON state, thus keeping voltage VA waveform low and voltage waveform VB high. The voltage supply from terminals 10 and 12 is therefore connected across the primary 42 of transformer T 1 and the secondary winding load currents are reflected to the T 1 primary winding 42 , as well as to inductances L 1 and L 2 . During this time, diodes D 1 , D 2 , D 3 , and D 4 , as well as FETs Q 1 and Q 4 , remain non-conducting.

During transition time T 6 , between periods P 5 and P 6 , FET switch Q 2 is controlled to an OFF state, resulting in a linear transition to a high state of voltage waveform VA, thereby causing diode element DQ 1 , of FET Q 1 , to conduct. As may be observed, FET Q 3 remains conducting while diodes D 1 , D 2 , D 3 , and D 4 , as well as FETs Q 1 and Q 4 , remain non-conducting.

FET switch Q 3 remains controlled to an ON state, during time period P 6 , resulting in keeping the voltage VB at junction point 38 high. The voltage VA at junction point 30 remains high as secondary winding 46 load currents reflected to the T 1 primary winding 42 drive diode element DQ 1 , of FET Q 1 , into conduction, although FET Q 1 itself remains non-conducting. Also, diodes D 1 , D 2 , D 3 , and D 4 , as well as FETs Q 2 and Q 4 , are non-conducting.

In the transition time T 7 , between period P 6 and a new period P 1 , FET switch Q 3 is controlled to an OFF state, resulting in a voltage waveform VB resonant transition to a low state and causing diode element DQ 4 , of FET Q 4 , to conduct. FET switch Q 4 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 4 . Also at this time, FET switch Q 1 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 1 . The voltage supply of terminals 10 and 12 is therefore connected across the primary winding 42 of transformer T 1 and the secondary winding rectifier reverse recovery and load currents are reflected to the T 1 primary winding 42 and to inductances L 1 and L 2 .

This results in diodes D 1 and D 4 conducting the T 1 secondary rectifier reverse recovery current. Diode elements DQ 1 and DQ 4 , as well as FETs Q 1 and Q 4 , are conducting, while diodes D 2 and D 3 , along with FETs Q 2 and Q 3 , are in a non-conducting state.

As mentioned previously, the circuit operation is slightly different when the second primary clamp circuit comprising diodes D 3 , D 4 and inductance L 2 is not installed. This operational difference only occurs during time periods P 4 through P 6 . The benefit with this configuration is the reduction in number of parts, although the physical size required of a single inductance will increase over that required with two clamp circuits.

During time period P 4 , FET switch Q 2 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 2 . Voltage waveform VA remains low and voltage VB remains high. The voltage supply is therefore connected across the primary 42 of transformer T 1 and the load currents in secondary winding 46 are reflected to the T 1 primary winding. Inductance L 1 is energized with reflected T 1 secondary winding rectifier reverse recovery current and, additionally, the load current. This results in diode element D 2 conducting the T 1 secondary winding rectifier reverse recovery current. As stated previously, diode D 1 and FETs Q 1 and Q 4 are non-conducting during this period.

During the T 5 transition time period from P 4 to P 5 , diode D 2 switches to a non-conducting state as reflected T 1 secondary winding load current increases to match the current in inductance L 1 . The remaining components remain in the state of time period P 4 .

During time period P 5 , FET switches Q 2 and Q 3 remain controlled to ON states keeping voltage VA low and voltage VB high, as occurred in the previous description. The voltage supply is therefore connected across the primary winding 42 of transformer T 1 and the secondary winding load currents are reflected to the T 1 primary winding 42 and inductance L 1 .

During transition time T 6 , between periods P 5 and P 6 , FET switch Q 2 is controlled to an OFF state, resulting in voltage waveforms VA linear transition to a high state, thereby causing diode element DQ 1 , of FET Q 1 , to conduct. As may be observed, FET Q 3 remains conducting while diodes D 1 , D 2 , as well as FETs Q 1 and Q 4 , remain non-conducting.

In a manner similar to the previously discussed time period P 6 , FET switch Q 3 remains controlled to an ON state, resulting in keeping the voltage VB at junction point 38 high. The voltage VA at junction point 30 remains high as secondary winding 46 load currents reflected to the T 1 primary winding 42 drive diode element DQ 1 , of FET Q 1 , into conduction, although FET Q 1 itself remains non-conducting. Also, diodes D 1 and D 2 , as well as FETs Q 2 and Q 4 , are non-conducting.

In the transition T 7 , between period P 6 and a new period P 1 , FET switch Q 3 is controlled to an OFF state, resulting in a voltage waveform VB resonant transition to a low state and causing diode element DQ 4 , of FET Q 4 , to conduct. FET switch Q 4 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 4 . Also at this time, FET switch Q 1 is controlled to an ON state with ZVS and takes over conduction from diode element DQ 1 . The voltage supply of terminals 10 and 12 is therefore connected across the primary winding 42 of transformer T 1 and the secondary winding rectifier reverse recovery and load currents are reflected to the T 1 primary winding 42 and to inductance L 1 . This results in diode D 1 conducting the T 1 secondary rectifier reverse recovery current. Diode element FET Q 2 remains non-conducting, as does diode D 2 .

From an understanding of the operation described above, it will be apparent that the operation of this circuit is generally similar to prior art phase shifted full bridge ZVS DC/DC converters. However, the simpler PWM control scheme and interaction of the components in the rectifier and filter block 48 with the primary clamp circuits results in less switch stress at light duty and minimizes reverse current spikes better than prior art circuits. From the discussion, it may be observed that the primary clamp circuit operates to minimize and circulate the reverse recovery switching currents generated by the output rectifiers and use this energy to supply current to output loads. As is known, prior art circuits had to use snubbing circuits to reduce the detrimental voltage breakdown effects of these transition time characteristics that are minimized by the primary clamp. Since the snubbing circuits act to dissipate this energy in the form of heat, energy is wasted. The present invention does not require such snubbing circuits, while remaining more energy efficient than the known prior art.

It should be realized, however, that, while snubbing circuits are not required, the present inventive circuit can include snubbing circuits to even further reduce emi of the converter as compared to the converter without a snubbing circuit.

Although the invention has been described with reference to a specific embodiment, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the claims will cover any such modifications or embodiments that fall within the true scope and spirit of the invention.