Integrated circuit memory devices providing per-bit redundancy and methods of operating same

This application claims the benefit of Korean Application No. 2001-7276, filed Feb. 14, 2001, the disclosure of which is hereby incorporated herein by reference.

The present invention relates to integrated circuit memory devices, and more particularly, to integrated circuit memory devices with redundant cells and methods of operation thereof.

Integrated circuit memory devices commonly include spare memory cells, i.e., redundant memory cells, which are used to replace primary (“normal”) memory cells that are defective. In some conventional memory devices, if at least one primary memory cell connected to a column select line CSL is defective, a column redundancy scheme is used, wherein the column select line CSL is replaced with a spare column select line SCSL. In other words, all memory cells connected to the column select line CSL are replaced with spare memory cells connected to the spare column select line SCSL, even if only one memory cell connected to the column select line is defective.

FIG. 1 shows a conventional one-to-one dedicated column redundancy scheme. Referring to FIG. 1, input/output blocks 11 and 13 each include a plurality of memory cells, column select lines CSL 11 , CSL 12 , CSL 21 , CSL 22 connected to the plurality of memory cells, and spare column select lines SCSL 11 , SCSL 12 , SCSL 21 , SCSL 22 . The column select lines CSL 11 , CSL 12 , CSL 21 , CSL 22 are connected to primary memory cells for normal operation of the primary memory cells. The spare column select lines SCSL 11 , SCSL 12 , SCSL 21 , SCSL 22 , which are connected to spare memory cells, i.e., redundant memory cells, are for used to replace defective memory cells.

The input/output block 11 includes one local input/output line LIO 1 and one global input/output line GIO 1 , and the input/output block 13 includes one local input/output line LIO 2 and one global input/output line GIO 2 . The local input/output line LIO 1 and the global input/output line GIO 1 input and output data into memory cells in the input/output block 11 , and the local input/output line LIO 2 and the global input/output line GIO 2 input and output data into memory cells in the input/output block 13 .

In the one-to-one redundancy scheme shown in FIG. 1, if a column select line CSL 11 in the input/output block 11 is defective, i.e., if at least one memory cell M 1 connected to the column select line CSL 11 is defective, the column select line CSL 11 is replaced with a spare column select line SCSL 11 . If a column select line CSL 21 in the input/output block 13 is defective, i.e., at least one memory cell connected to the column select line CSL 21 is defective, the column select line CSL 21 is replaced with a spare select line SCSL 21 . In other words, all memory cells connected to a defective column select line are replaced with spare memory cells connected to a spare column select line, even if only one memory cell connected to the column select line is defective.

In the one-to-one column redundancy scheme shown in FIG. 1, defective column select lines in a predetermined input/output block are replaced with only spare column select lines in the same input/output block. Because of this, the number of repairable column select lines in the input/output block depends on the number of spare column select lines available in the same input/output block.

FIG. 2 shows a conventional dataline column redundancy scheme. Referring to FIG. 2, in the dataline column redundancy scheme, input/output blocks 21 and 23 do not include spare column select lines. A redundant input/output block 25 includes spare column select lines.

The input/output block 21 includes one local input/output line LIO 1 , and the input/output block 23 includes one local input/output line LIO 2 . The redundant input/output block 25 also includes one local input/output line LIO 3 . The input/output blocks 21 and 23 and the redundant input/output block 25 share a global input/output line GIO.

Data is input into and output from memory cells in the input/output block 21 via the local input/output line LIO 1 and the shared input/output line GIO, and data is input into and output from memory cells in the input/output block 23 via the local input/output line LIO 2 and the shared input/output line GIO. Data is input into and output from memory cells in the redundant input/output block 25 via the local input/output line LIO 3 and the shared global input/output line GIO.

In the dataline column redundancy scheme shown in FIG. 2, if column select lines CSL 11 and CSL 12 in the input/output block 21 are defective, the column select lines CSL 11 and CSL 12 are replaced with spare column select lines SCSL 1 and SCSL 2 in the redundant input/output block 25 . If column select lines CSL 21 , CSL 22 , and CSL 23 in the input/output block 23 are defective, the column select lines CSL 21 , CSL 22 , CSL 23 are replaced with spare column select lines SCSL 3 , SCSL 4 , and SCSL 5 in the redundant input/output block 25 .

Accordingly, in the dataline column redundancy scheme shown in FIG. 2, defective column select lines in the input/output blocks are replaced with spare column select lines in the redundant input/output block. Therefore, repair efficiency and flexibility may be improved to some extent. However, like the column redundancy scheme shown in FIG. 1, all memory cells connected to a column select line are replaced with the spare memory cells connected to a spare column select line even if only one memory cell connected to the defective column select line is defective.

According to some embodiments of the present invention, an integrated circuit memory device includes a plurality of memory cells arranged as a plurality of blocks, each of the blocks including a plurality of primary memory cells that are coupled and decoupled to and from respective input/output lines responsive to a primary column select line and a plurality of redundant memory cells that are coupled and decoupled to and from respective ones of the input/output lines responsive to a redundant column select line. A column select circuit is coupled to the primary column select lines and to the redundant column select lines. The column select circuit drives a first primary column select line associated with a primary memory cell in a first block responsive to application of a first column address. The column select circuit simultaneously drives the first primary column select line and a first redundant column select line associated with a first redundant memory cell in a second block responsive to application of a second column address. The memory device further includes a plurality of sense amplifiers, and an input/output control circuit that is configurable to selectively connect the input/output lines to the sense amplifiers such that the first primary memory cell is coupled to a sense amplifier responsive to application of the first column address and such that the first redundant memory cell is coupled to the sense amplifier responsive to application of the second column address. The select circuit and the input/output control circuit may be operative to replace an individual primary memory cell with an individual redundant memory cell. In some embodiments, the input/output control circuit includes a plurality of switches operative to couple and decouple the input/output lines to and from the sense amplifiers. A switch control circuit controls the plurality of switches. The control circuit may be fuse-programmable.

Related operating methods are also described.

FIGS. 1 and 2 are schematic diagrams illustrating conventional integrated circuit memory devices.

FIG. 3 is a schematic diagram illustrating a memory device according to some embodiments of the present invention.

FIG. 4 is a schematic diagram illustrating a memory device according to further embodiments of the present invention.

FIG. 5 is a schematic diagram illustrating a memory device according to still further embodiments of the present invention.

FIG. 6 is a schematic diagram illustrating a switch control circuit according to further embodiments of the present invention.

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which typical embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

Referring to FIG. 3, in an integrated circuit memory device according to the present invention, input/output blocks 31 , 32 , and 33 are divided into first blocks 31 L, 32 L, and 33 L and second blocks 31 R, 32 R, and 33 R, respectively. It will be understood that the input/output blocks 31 , 32 , and 33 may be divided into three or more blocks.

The first blocks 31 L, 32 L, and 33 L and the second blocks 31 R, 32 R, and 33 R each include a plurality of memory cells, column select lines CSL 1 L, CSL 2 L, CSL 2 R, SCSL 2 R connected to the plurality of memory cells, and spare column select lines SCSL 1 L, SCSL 1 R, SCSL 2 L, SCSL 3 L, SCSL 3 R. The column select lines CSL 1 L, CSL 2 L, CSL 2 R, SCSL 2 R are connected to primary memory cells for normal operation of the primary memory cells. The spare column select lines SCSL 1 L, SCSL 1 R, SCSL 2 L, SCSL 3 L, SCSL 3 R are connected to spare memory cells, i.e., redundant memory cells, to replace defective memory cells.

The input/output block 31 includes a local input/output line LIO 1 L and a global input/output line GIO 1 L for a first block 31 L, and a local input/output line LIO 1 R and a global input/output line GIO 1 R for a second block 31 R. The input/output block 32 includes a local input/output line LIO 2 L and a global input/output line GIO 2 L for a first block 32 L, and a local input/output line LIO 2 R and a global input/output line GIO 2 R for a second block 32 R. The input/output block 33 includes a local input/output line LIO 3 L and a global input/output line GIO 3 L for a first block 33 L, and a local input/output line LIO 3 R and a global input/output line GIO 3 R for a second block 33 R.

In the input/output block 31 , data is input into and output from memory cells in the first block 31 L via the local input/output line LIO 1 L and the global input/output line GIO 1 L, and data is input into memory cells in the second block 31 R via the local input/output line LIO 1 R and the global input/output line GIO 1 R. In the input/output block 32 , data is input into and output from memory cells in the first block 32 L via the local input/output line LIO 2 L and the global input/output line GIO 2 L, and data is input into memory cells in the second block 32 R via the local input/output line LIO 2 R and the global input/output line GIO 2 R. In the input/output block 33 , data is input into and output from memory cells in the first block 33 L via the local input/output line LIO 3 L and the global input/output line GIO 3 L, and data is input into memory cells in the second block 33 R via the local input/output line LIO 3 R and the global input/output line GIO 3 R.

If a cell associated with the column select line CSL 2 L in the first block 32 L of the input/output block 32 is defective, the column select line CSL 2 L is not replaced with a spare column select line SCSL 2 L in its input/output block, i.e., the first block 32 L of the input/output block 32 . Instead, the column select line may be replaced with the spare column select line SCSL 2 R in the second block 32 R of the input/output block 32 or the spare column select line SCSL 1 R in the second block 31 R of the input/output block 31 adjacent to the input/output block 32 .

This allows a defective memory cell of memory cells connected to the defective column select line CSL 2 L to be replaced with a spare memory cell connected to the spare column select line, while primary memory cells of memory cells connected to the defective column select line CSL 2 L are not replaced. In particular, the primary column select line (associated with the defective cell) and the spare column select line are simultaneously activated, such that the memory cells connected to the primary column select line are used, except when the defective cell is to be accessed.

If a memory cell associated with a column select line CSL 2 R in the second block 32 R of the input/output 32 is defective, the column select line CSL 2 R is not replaced with a spare column select line SCSL 2 R in its input/output block, i.e., the second block 32 R of the input/output block 32 . Instead, the column select line CSL 2 R is replaced with the column select line SCSL 2 L in the first block 32 L of the input/output block 32 or a spare column select line SCSL 3 L in the first block 33 L of the input/output block 33 adjacent to the input/output block 32 . Only a defective memory cell of memory cells connected to the defective column select line CSL 2 R is replaced with a spare memory cell connected to the spare column select line, while non-defective memory cells of memory cells connected to the defective column select line CSL 2 R are not replaced. The defective column select line CSL 2 R and the spare column select line are simultaneously activated, such that the memory cells connected to the primary column select line are used, except when the defective cell is to be accessed. If the input/output blocks 31 and 33 have defective cells, defective memory cells may be replaced with spare memory cells as described above.

A integrated circuit memory device according to embodiments of the present invention illustrated in FIG. 3 includes switches S 11 , S 12 , S 13 , S 14 , S 21 , S 22 , S 23 , S 24 , S 31 , S 32 , S 33 , S 34 , a switch controller (shown in FIG. 6) for controlling switches S 11 through S 34 , and input/output sense amplifiers 34 , 35 , and 36 . The input/output sense amplifiers 34 , 35 , and 36 are each connected to corresponding input/output pins DQ 1 , DQ 2 , and DQ 3 .

The switches S 11 , S 12 , S 13 , S 14 , S 21 , S 22 , S 23 , S 24 , S 31 , S 32 , S 33 , S 34 control the connection between global input/output lines GIO and the input/output sense amplifiers 34 , 35 , and 36 . In particular, as described above, since the primary column select line having a defective cell and the spare column select line are simultaneously activated, the switches S 11 , S 12 , S 13 , S 14 , S 21 , S 22 , S 23 , S 24 , S 31 , S 32 , S 33 , S 34 can simultaneously form a data path through the defective column select line and a data path through the spare column select line toward a input/output sense amplifier.

For example, a path path 2 from the global input/output line GIO 2 L corresponding to a column select line CSL 2 L, and a path path 1 from the global input/output line GIO 1 R corresponding to the spare column select line SCSL 1 R can be simultaneously formed to the input/output sense amplifier 35 when the column select line CSL 2 L is treated as defective and replaced with the spare column select line SCSL 1 R. A path path 2 from the global input/output line GIO 2 L corresponding to the column select line CSL 2 L and a path path 3 from the global input/output line GIO 2 R corresponding to the spare column select line SCSL 2 R can be simultaneously formed to the input/output sense amplifier 35 if the column select line CSL 2 L is treated as defective and replaced with the spare column select line SCSL 2 R.

FIG. 4 is a diagram explaining how defective memory cells may be replaced with spare memory cells in an integrated circuit memory device according to embodiments of the present invention shown in FIG. 3 . CSL 2 L 1 , CSL 2 L 2 , and CSL 2 L 3 denote column select lines in the first block 32 L of the input/output block 32 shown in FIG. 3, and SCSL 2 R denotes a spare column select line in the second block 32 R of the input/output block 32 . The column select lines CSL 2 LI, CSL 2 L 2 , and CSL 2 L 3 and the spare column select line SCSL 2 R are each connected to four memory cells.

If the third memory cell M 13 of four memory cells M 11 -M 14 connected to the column select line CSL 2 L 1 is defective, three primary memory cells M 11 , M 12 , and M 14 are connected to a first sense amplifier 35 - 1 by switches S 41 , S 42 , and S 44 , and a third spare memory cell SM 3 , which is connected to the column select line SCSL 2 R, instead of the defective memory cell M 13 , is connected to the first sense amplifier 35 - 1 by a switch S 43 . If the first memory cell M 21 of four memory cells M 21 -M 24 connected to the column select line CSL 2 L 2 is defective, three primary memory cells M 22 , M 23 , and M 24 are connected to a second sense amplifier 35 - 2 by switches S 46 , S 47 , and S 48 , and a first spare memory cell SM 1 , which is connected to the spare column select line SCSL 2 R, instead of the defective memory cell M 21 , is connected to the second sense amplifier 35 - 2 by a switch S 45 . If the second and fourth memory cell M 32 and M 34 of four memory cells M 31 -M 34 connected to the column select line CSL 2 L 3 are defective, two primary memory cells M 31 and M 33 are connected to a third sense amplifier 35 - 3 by switches S 49 and S 51 , respectively, and spare memory cells SM 2 and SM 4 , which are connected to the spare column select line SCSL 2 R, instead of the defective memory cells M 32 and M 34 , are connected to the third sense amplifier 35 - 3 by switches S 50 and S 52 , respectively. Therefore, defective memory cells connected to one or more column select lines may be replaced with spare memory cells connected to one spare column select line an a per bit basis.

FIG. 5 is a detailed circuit diagram of a portion of the circuit shown in FIGS. 3 and 4. The column select line CSL 2 L 1 and the spare column select line SCSL 2 R are simultaneously activated by a column driver (not shown). Switches S 22 - 1 , S 22 - 2 , and S 23 - 3 are turned on, and switches S 22 - 3 , S 23 - 1 , S 23 - 2 , and S 23 - 4 are turned off. As a result, global input/output lines GL 1 , GL 2 , and GL 4 corresponding to the primary memory cells M 11 , M 12 , and M 14 and a global input/output line GR 3 corresponding to the spare memory cell SM 3 are connected to input/output sense amplifiers 35 - 1 a , 35 - 1 b , 35 - 1 c , and 35 - 1 d.

Accordingly, data of the primary memory cells M 11 , M 12 , M 14 is transmitted to the input/output sense amplifiers 35 - 1 a , 35 - 1 b , 35 - 1 c , and 35 - 1 d via local input/output lines LL 1 , LL 2 , and LL 4 and global input/output lines GL 1 , GL 2 , and GL 4 . However, data of the defective memory cell M 13 is not transmitted to the input/output sense amplifier 35 - 1 c . Instead, data of the spare memory cell SM 3 is transmitted to the input/output sense amplifier 35 - 1 c via a local input/output line LR 3 and a global input/output line GR 3 . The defective memory cell M 13 is replaced with the spare memory cell SM 3 .

FIG. 6 is a detailed circuit diagram of a switching controller that may be used with the circuit of FIG. 5 . Referring to FIG. 6, the switching controller includes a plurality of control signal generating circuits 61 , 62 , 63 , 64 . The control signal generating circuits 61 , 62 , 63 , 64 each include AND gates AN 1 , AN 2 , and AN 3 , an OR gate, and inverters IN 1 and IN 2 . F (or F′) is a signal representing the position of an input/output block having defective column select lines. F (or F′) is logic “low” if a predetermined input/output block has defective column select lines and logic “high” if an input/output block adjacent to the predetermined input/output block has defective column select lines. S 1 (or S 1 ′) is a signal which is logic “high” if the first memory cell connected to a defective column select line is defective and an applied column address corresponds to the first memory cell, and is logic “low” otherwise. S 2 (or S 2 ′) is a signal which is logic “high” if the second memory cell connected to the column select line is defective and an applied column address corresponds to the second memory cell, and is logic “low” otherwise. S 3 (or S 3 ′) is a signal which is logic “high” if the third memory cell connected to the column select line is defective and an applied column address corresponds to the third memory cell, and is logic “low” otherwise. S 4 (or S 4 ′) is a signal which is logic “high” if the fourth memory cell connected to the column select line is defective and an applied column address corresponds to the fourth memory cell, and is logic “low” otherwise.

Signals F, F′, S 1 , S 2 , S 3 , S 4 , S 1 ′ S 2 ′, S 3 ′, S 4 ′ may be generated, for example, by programming fuses in a fuse block (not shown). Such fuse blocks are well known to one skilled in the art; therefore, discussion of detailed operation of the fuse block is omitted.

Column most significant bit (CMSB) is the most significant bit of the column address and represents the positions of first and second blocks in an input/output block. In particular, CMSB is logic “high” if representing the position of the first block in the input/output block and logic “low” if representing the position of the second block in the input/output block.

The operation of the switching controller and the overall operation of the circuit shown in FIG. 5 will be described with reference to FIGS. 5 and 6. F is set to logic “low,” S 3 is logic “low”, and S 1 , S 2 , and S 4 are all logic “high” if the third memory cell M 13 connected to the column select line CSL 2 L 1 is defective and the column address applied from the outside is for the third memory cell M 13 . Also, CMSB is logic “high”.

As a result, switch control signals C 11 , C 12 , C 13 , C 14 are logic “low” and inverse switch control signals C 11 B, C 12 B, C 13 B, C 14 B are logic “high”. Switch control signals C 21 , C 22 , C 24 are logic “high” and inverse switch control signals C 21 B, C 22 B, C 23 B are logic “low”. Also, switch control signal C 23 is logic “low” and an inverse switch signal C 23 B is logic “high.” Thus, switches S 21 - 1 , S 21 - 2 , S 21 - 3 , and S 21 - 4 are turned off, switches S 22 - 1 , S 22 - 2 , and S 22 - 4 are turned on, and switch S 22 - 3 is turned off. As a result, global input/output lines GL 1 , GL 2 , and GL 4 corresponding to primary memory cells M 11 , M 12 , M 14 are connected to input/output sense amplifiers 35 - 1 a , 35 - 1 b , 35 - 1 d.

Switch control signals C 11 ′, C 12 ′, C 13 ′, C 14 ′ are all logic “low” and inverse switch control signals C 11 ′B, C 12 ′B, C 13 ′B, C 14 ′B are all logic “high”. Switch control signals C 21 ′, C 22 ′, C 24 ′ are logic “low” and inverse switch control signals C 21 ′B, C 22 ′B, C 24 ′B are logic “high.” Switch control signal C 23 ′ is logic “high” and inverse switch control signal C 23 ′B is logic “low”. Thus, switches S 24 - 1 , S 24 - 2 , S 24 - 3 , S 24 - 4 are turned off, switches S 23 - 1 , S 23 - 2 , S 23 - 4 are turned off and switch S 23 - 3 is turned on. As a result, the global input/output line GR 3 corresponding to the spare memory cell SM 3 is connected to the input/output sense amplifier 35 - 1 c.

Accordingly, as described above, data of the primary memory cells M 11 , M 12 , and M 14 is transmitted to the input/output sense amplifier 35 - 1 a , 35 - 1 b , and 35 - 1 d via the local input/output lines LL 1 , LL 2 , and LL 4 and the global input/output lines GL 1 , GL 2 , and GL 4 . However, data of the defective memory cell M 13 is not transmitted to the input/output sense amplifier 35 - 1 c . Instead, data of the spare memory cell SM 13 is transmitted to the input/output sense amplifier 35 - 1 c via the local input/output line LR 3 and the global input/output line GR 3 . The defective memory cell M 13 is thus replaced with the spare memory cell SM 3 .

As described above, in the integrated circuit memory device according to embodiments of the present invention, defective memory cells connected to one column select line may be replaced with spare memory cells connected to one spare column select line on a per bit basis. Also, defective memory cells connected to one or more column select lines may be replaced with spare memory cells connected to one spare column select line. Thus, repair efficiency and flexibility can be greatly improved.

In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.