Multi-phase converter with balanced currents

This application claims the benefit of U.S. Provisional Application No. 60/151,982, filed Sep. 1, 1999.

This reissue application, U.S. Ser. No. 10 / 044 , 479 , is the parent of Reissue Continuation application Ser. No. 10 / 375 , 926 , filed Feb. 26 , 2003 .

The present invention relates to an apparatus and method for balancing the individual channel currents in a multi-phase DC/DC converter.

There are no known prior art devices or methods that specifically balance the channel currents of multi-phase converters.

Personal computers have direct current (DC) power supplies to regulate their operating voltage and current. Early personal computers operated their circuits at ±5 volts and drew several amps of current. In order to speed-up performance, operating voltages were dropped to the range of ±1.5 to 1.0 volts and currents have risen to 50 or more amps. It is more economical to provide the 50 or more amps from several power sources rather than from a single source. This has led many power supply manufacturers to provide multi-phase converters with two or more current channels. While there are more component parts in multi-phase systems, the parts themselves are smaller and typically less expensive than the high-power parts which must be used in a single-converter having similar current capabilities.

When multi-phase converters supply the same load there is often a voltage mismatch between the channels. If two or more channels have even slightly different output voltages, current will flow mostly from the channels with the highest voltage. Some converters have the ability to sink as well as source output current. In those converters, current may flow from one channel to another, regardless of load current. This can lead to excessive power dissipation. Additionally, the load that these converters supply must be limited below the combined full load capability of the individual channel.

Without the capability to share the load current, each converter channel provides a current proportional to the average phase voltage and the net converter resistance. The average phase voltage is approximated by:

V PH =(V IN −V UP )·D−V LOW (1−D)

where:

V IN is the input voltage,

V UP is the voltage drop across the upper switch,

V LOW is the voltage across the lower switch, and

D is the duty cycle.

The net converter resistance includes the summation of the inductor winding resistance, any trace resistance, and the time multiplexed resistance of the upper and lower power switches.

In multi-phase converters, the ability to equally share the load current depends upon the matching of parameters and components between each of the phases or channels. Current sharing is particularly sensitive to any duty cycle mismatch between channels. Matching the duty cycle of multiple phases is difficult because of inherent component mismatches that can induce timing errors. As a result, any channel may be forced to carry significantly more than its proportional share of the load current. For example, in a four-phase converter with four converter channels, one channel may carry 40% of the load current while the other channels each carry 20%, rather than each channel carrying the ideal 25%. Thus, each channel must be sized to carry at least 40% of the projected output current, or 15% more than its proportionate share. Designing each of the four channels for 40% of the projected output current, rather than for 25% of the projected output current, requires the use of oversized power output transistors and passive components, such as, for example, inductors and resistors, in order for each channel to safely conduct a higher proportion of load current. Since the distribution of the load varies, each power transistor must be larger than needed for the total load. However, if the load is more evenly distributed smaller transistors as well as smaller passive components can be used to achieve the same load current capability as oversized prior art systems. Smaller transistor and passive components are less expensive and more efficient than larger, higher-power components.

Therefore, what is needed in the art is a multi-phase converter which equally shares the load current between each of the phases or channels.

Furthermore, what is needed in the art is a multi-phase converter which uses smaller transistors and smaller passive components to produce a given load current capability, thereby making it less expensive to produce and sell.

The present invention provides an apparatus and method for balancing the channel currents in a multi-phase DC/DC converter.

The invention comprises, in one form thereof, a multi-phase DC/DC converter having an output voltage and including a plurality of converter channels. Each converter channel includes a converter channel input and a converter channel output. Each converter channel is configured for generating a converter channel current and for adjusting said converter channel current in response to a control signal electrically connected to each converter channel input. A control circuit generates an error signal representative of a comparison of the converter output voltage to a reference voltage. The control circuit includes a plurality of control circuit channels, each of which correspond to a converter channel. Each control circuit channel generates a channel current signal representative of a corresponding converter channel current, and generates a differential channel current signal representative of a comparison of the channel current signal to an average current signal. The average current signal is representative of an overall average current for the converter channels. Each control circuit channel generates a differential error signal representative of a comparison of the error signal to the differential channel current signal. Each control circuit channel includes a pulse width modulator having a ramp input and a control input. The control input is electrically connected to the differential error signal. The pulse width modulator generates the control signal based upon the differential error signal. The control signal is electrically coupled to a corresponding converter channel input. The control circuit generates the average current signal.

The above-mentioned and other features and advantages of this invention, and the manner of attaining them, will become apparent and be better understood by reference to the following description of one embodiment of the invention in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a four-phase, four-channel converter; and

FIG. 2 shows the control circuit for the four-channel converter system in FIG. 1 .

Corresponding reference characters indicate corresponding parts throughout the several views. The exemplification set out herein illustrates one preferred embodiment of the invention, in one form, and such exemplification is not to be construed as limiting the scope of the invention in any manner.

Generally, the multi-phase converter of the present invention has multiple converter channels to source the load current. Each converter channel can be considered as an independent converter, and is controlled by a pulse-width modulated (PWM) signal. For this discussion, each converter channel is a buck converter or synchronous-rectified buck converter. The converters may share a common output capacitance.

Referring now to the drawings, and particularly to FIG. 1, there is shown one embodiment of a 4-channel multi-phase converter 10 of the present invention. Converter 10 drives load 12 and includes control circuit 14 . Interconnected electrically between load 12 and control circuit 14 are, for example, four synchronous-rectified buck channels or converter channels 18 a, 18 b, 18 c, 18 d. More particularly, each converter channel 18 a, 18 b, 18 c, 18 d includes a respective converter channel input 22 a, 22 b, 22 c, 22 d. Control circuit 14 includes four control circuit outputs 14 a, 14 b, 14 c, 14 d, each of which are electrically connected to a respective one of converter channel inputs 22 a, 22 b, 22 c, 22 d. Each converter channel 18 a, 18 b, 18 c, 18 d further includes a respective converter channel output 24 a, 24 b, 24 c, 24 d, through which flows a respective converter channel current. Control circuit 14 provides at each output 14 a, 14 b, 14 c, 14 d, a separate and independent PWM signal, PWM 1 , PWM 2 , PWM 3 , PWM 4 , to each converter channel input 22 a, 22 b, 22 c, 22 d. The four PWM signals regulate the current flowing through each converter channel output 24 a, 24 b, 24 c, 24 d.

As will be described more particularly hereinafter, the output currents of converter channels 18 a, 18 b, 18 c, 18 d, are separately and individually fed back to control circuit 14 . The individual PWM signals PWM 1 , PWM 2 , PWM 3 , PWM 4 at each control circuit outputs 14 a, 14 b, 14 c, 14 d, respectively, are modified based at least in part upon the fed-back converter channel current. The modified or adjusted individual PWM signals PWM 1 , PWM 2 , PWM 3 , PWM 4 are provided to each converter channel input 22 a, 22 b, 22 c, 22 d. More particularly, control circuit 14 includes current feedback lines 28 a, 28 b, 28 c, 28 d which electrically connect a respective one of converter channel outputs 24 a, 24 b, 24 c, 24 d to a respective one of control circuit inputs 32 a, 32 b, 32 c, 32 d. Thus, each of current feedback lines 28 a, 28 b, 28 c, 28 d provide a current feedback path for each of the converter channel currents flowing through converter channels 18 a, 18 b, 18 c, and 18 d, respectively. Each of feedback lines 28 a, 28 b, 28 c, 28 d, are considered as forming a part of four separate control circuit channels.

It is preferred to use a feedback method that provides a separate feedback signal from each of converter channels 18 a, 18 b, 18 c, 18 d to each control circuit channel. The separate feedback signals are each proportional to the converter channel current being sourced by a corresponding converter channel. The operation of each channel 18 a, 18 b, 18 c, 18 d is then individually and separately adjusted on the basis of the fed-back converter channel current to balance the converter channel currents relative to each other. Providing to each control circuit channel a feedback signal that is proportional to the current being sourced by a corresponding converter channel eliminates issues with component mismatch between the converter channels. Generally, and as will be described with more particularity hereinafter, converter 10 subtracts from an error amplifier's output a signal that is proportional to the converter current imbalance existing between the converter channels to thereby correct for any imbalance between the converter currents.

Feed back path 34 electrically connects output 36 of converter 10 to feedback input 32 f of control circuit 14 . Control circuit 14 thus receives via feed back path 34 the voltage being supplied to load 12 .

Referring now to FIG. 2, control circuit 14 is shown in more detail. Generally, and as will be described with more particularity hereinafter, the converter channel current of each converter channel 18 a, 18 b, 18 c, 18 d is individually compared to the overall average converter channel current of all the converter channels 18 a, 18 b, 18 c, and 18 d. The current of each converter channel 18 a, 18 b, 18 c, 18 d is then individually and separately adjusted to bring it closer to the average and, therefore, making the converter channel current in each of converter channels 18 a, 18 b, 18 c, 18 d substantially equal to each other.

Error amplifier (E/A) 42 has a first input 32 f electrically connected via feedback path 34 to output 36 of converter 10 . E/A 42 compares the voltage at converter output 36 , or the load voltage, to a reference voltage REF electrically connected to input 42 a of error amplifier 42 . The output voltage VE/A appearing on output 42 b of E/A 42 increases when the voltage at output 36 of converter 10 is below the reference voltage applied to input 42 a of E/A 42 . Conversely, the output voltage VE/A appearing on output 42 b of E/A 42 decreases when the voltage at output 36 of converter 10 is above the reference voltage applied to input 42 a of E/A 42 . The current flowing from each converter channel output 24 a, 24 b, 24 c, 24 d flows through a series resistor (not shown) in each of current feedback paths 28 a, 28 b, 28 c, 28 d to thereby create V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 , respectively. Each of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 , is proportional to the individual converter channel current flowing through converter channel outputs 24 a, 24 b, 24 c, 24 d, respectively. Each of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 , is electrically connected to control circuit 14 via feedback paths 28 a, 28 b, 28 c, 28 d, respectively. However, it is to be understood that the series resistor may be integrated within control circuit 14 , in which case feedback paths 28 a, 28 b, 28 c, 28 d would deliver the converter channel currents flowing through converter channel outputs 24 a, 24 b, 24 c, 24 d, respectively, and in which case V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 would be created internally of control circuit 14 .

Summing circuit 44 includes inputs 44 a, 44 b, 44 c, 44 d, each of which are electrically connected to control circuit inputs 32 a, 32 b, 32 c, 32 d, thereby connecting inputs 44 a, 44 b, 44 c, 44 d of summing circuit 44 to V ISENSE1 , V ISENSE2 , V ISENSE3 , V ISENSE4 , respectively. Summing circuit 44 adds together each of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 , and produces a signal proportional to the sum of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 at output 44 f. Output 44 f of summing circuit 44 is electrically connected to input 46 a of scaling circuit 46 . Scaling circuit 46 scales (i.e., divides by 4) the sum of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 to thereby produce signal V average , which is proportional to the average of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 , at output 46 b.

Each control circuit channel includes a respective subtraction circuit 48 , 50 , 52 , 54 . Each of subtraction circuits 48 , 50 , 52 , 54 include inputs 48 a and 48 b, 50 a and 50 b, 52 a and 52 b, and 54 a and 54 b, respectively. Input 48 a of subtraction circuit 48 is electrically connected to input 32 a of control circuit 14 , thereby connecting input 48 a of subtraction circuit 48 to V ISENSE1 . Input 50 a of subtraction circuit 50 is electrically connected to input 32 b of control circuit 14 , thereby connecting input 50 a of subtraction circuit 48 to V ISENSE2 . Input 52 a of subtraction circuit 52 is electrically connected to input 32 c of control circuit 14 , thereby connecting input 52 a of subtraction circuit 48 to V ISENSE2 . Likewise, input 54 a of subtraction circuit 54 is electrically connected to input 32 d of control circuit 14 , thereby connecting input 54 a of subtraction circuit 48 to V ISENSE4 . Each input 48 b, 50 b, 52 b, and 54 b of subtraction circuits 48 , 50 , 52 , 54 , respectively, is electrically connected to output 46 b of scaling circuit 46 , thereby connecting each input 48 b, 50 b, 52 b, 54 b to V average . Each of the subtraction circuits 48 , 50 , 52 , 54 , subtracts V average from each of V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 . More particularly, subtraction circuit 48 subtracts V average from V ISENSE1 , subtraction circuit 50 subtracts V average from V ISENSE2 , subtraction circuit 52 subtracts V average from V ISENSE3 , and subtraction circuit 54 subtracts V average from V ISENSE4 . The results of the subtraction performed by each of subtraction amplifiers 48 , 50 , 52 , 54 represent the difference between the current flowing through a respective one of converter channels 18 a, 18 b, 18 c, 18 d and the average of the converter channel currents being sourced conjuctively by converter channels 18 a, 18 b, 18 c, 18 d (i.e., the value represented by V average ). Outputs 48 c, 50 c, 52 c, and 54 c of subtraction circuits 48 , 50 , 52 , 54 , respectively, are electrically connected to a respective one of compensation circuits G.

Each control circuit channel also includes a compensation circuit G 1 , G 2 , G 3 , G 4 . Each compensation circuit G 1 , G 2 , G 3 , G 4 performs current loop compensation functions, such as, for example, gain or filter functions to shape the current feedback wave, to achieve adequate current balancing, or to prevent current loop instability. Each compensation circuit G 1 , G 2 , G 3 , G 4 may include at least one pole and zero. The output of each compensation circuit G 1 , G 2 , G 3 , G 4 represents the difference between the current flowing through a respective one of converter channels 18 a, 18 b, 18 c, 18 d and the overall average of the converter channel currents being sourced conjunctively by converter channels 18 a, 18 b, 18 c, 18 d (i.e., the value represented by V average ), and is represented by signals ΔI 1 , ΔI 2 , ΔI 3 , ΔI 4 , respectively. Thus, signals ΔI 1 , ΔI 2 , ΔI 3 , ΔI 4 represent the difference between the overall average of the converter channel currents being sourced conjunctively by converter channels 18 a, 18 b, 18 c, 18 d (i.e., the value represented by V average ) and the actual value of the current flowing within converter channels 18 a, 18 b, 18 c, and 18 d, respectively. More particularly, and for example, ΔI 1 represents the difference between the overall average of the converter channel currents being sourced conjunctively by channels 18 a, 18 b, 18 c, 18 d, and the actual value of the converter channel current flowing within converter channel 18 a. Likewise, and as a further example, ΔI 2 represents the difference between the overall average of the converter channel currents being sourced conjunctively by converter channels 18 a, 18 b, 18 c, 18 d, and the actual value of the current flowing within converter channel 18 b. Ideally, each of the ΔI 1 , ΔI 2 , ΔI 3 , and ΔI 4 signals will be zero, thus indicating equal converter channel currents are flowing through each of converter channels 18 a, 18 b, 18 c, 18 d. Signals ΔI 1 , ΔI 2 , ΔI 3 , ΔI 4 are input into subtraction circuits 58 , 60 , 62 , 64 , respectively.

Each control circuit channel includes a subtraction circuit 58 , 60 , 62 , 64 . Each of subtraction circuits 58 , 60 , 62 , 64 include respective inputs 58 a, and 58 b, 60 a and 60 b, 62 a and 62 b, and 64 a and 64 b. Inputs 58 a, 60 a, 62 a, and 64 a are electrically connected to G 1 , G 2 , G 3 , and G 4 , respectively, thereby connecting each of subtraction circuits 58 , 60 , 62 , and 64 to signals ΔI 1 , ΔI 2 , ΔI 3 , ΔI 4 , respectively. Each of inputs 5 b, 60 b, 62 b, and 64 b, are electrically connected to output 42 b of E/A 42 , thereby connecting each subtraction circuit 58 , 60 , 62 , and 64 to VE/A. As described hereinabove, VE/A increases when the voltage at output 36 of converter 10 is below the reference voltage REF applied to input 42 a of E/A 42 . Conversely, the output voltage VE/A of output 42 b decreases when the voltage at output 36 of converter 10 is above the reference voltage REF applied to input 42 a of E/A 42 . Difference or subtraction circuits 58 , 60 , 62 , and 64 compare a respective one of ΔI 1 , ΔI 2 , ΔI 3 , and ΔI 4 to signal VE/A. Outputs 58 c, 60 c, 62 c, and 64 c of subtraction circuits 58 , 60 , 62 , 64 , respectively, are electrically connected to a respective one of PWM amplifiers 68 , 70 , 72 , 74 .

Each control circuit channel includes a PWM amplifier 68 , 70 , 72 , 74 . Each of PWM amplifiers 68 , 70 , 72 , 74 include inputs 68 a and 68 b, 70 a and 70 b, 72 a and 72 b, and 74 a and 74 b, respectively. Inputs 68 a, 70 a, 72 a, 74 a are electrically connected to outputs 58 c, 60 c, 62 c, 64 c, respectively, of subtraction circuits 58 , 60 , 62 , 64 , respectively. Each input 68 b, 70 b, 72 b, 74 b is connected to a reference PWM waveform. PWM amplifiers 68 , 70 , 72 , 74 modify the reference PWM waveform dependent at least in part upon inputs 68 a, 70 a, 72 a, 74 a, respectively. More particularly, the pulse width of the reference PWM will be individually and separately modified by each PWM amplifier 68 , 70 , 72 , 74 dependent at least in part upon a respective one of inputs 68 a, 70 a, 72 a, 74 a. The individually and separately modified reference PWM waveforms appear at control circuit outputs 14 a, 14 b, 14 c, 14 d of PWM amplifiers 68 , 70 , 72 , 74 , respectively, as signal PWM 1 , PWM 2 , PWM 3 , and PWM 4 , respectively. The modification of the reference PWM waveform by each PWM amplifier 68 , 70 , 72 , and 74 is in such a direction as to bring the converter channel current of each converter channel 18 a, 18 b, 18 c, 18 d closer to the average output current, V average . More particularly, the pulse width of each of signals PWM 1 , PWM 2 , PWM 3 , PWM 4 , will be modified (i.e. shortened or lengthened) in such a direction as to bring the converter channel current of each converter channel 18 a, 18 b, 18 c, 18 d closer to the average output current, V average . Each signal PWM 1 , PWM 2 , PWM 3 , and PWM 4 of PWM amplifiers 68 , 70 , 72 , 74 , respectively, is electrically connected to a respective one of converter channel inputs 22 a, 22 b, 22 c, and 22 d, respectively, as described hereinabove.

In use, when converter 10 is operating under, for example, the condition that converter channel 18 a is carrying a converter channel current that is higher than the average of all converter channel currents, as represented by V average , subtraction circuit 48 will generate a positive ΔI 1 signal. This positive ΔI 1 is input into subtraction circuit 58 . Subtraction circuit 58 subtracts the positive ΔI 1 signal from VE/A, i.e. the output of error amplifier 42 , thereby reducing output 58 c, which is electrically connected to input 68 a of PWM 68 . In response, PWM 68 reduces the pulse width of PWM 1 at output 14 a. The reduction in pulse width of PWM 1 reduces the converter channel current flowing through converter channel 18 a to a value closer to the average of all converter channel currents, as represented by V average . Conversely, when converter 10 is operating under, for example, the condition that converter channel 18 b is carrying a converter channel current that is lower than the average of all converter channel currents, as represented by V average , a negative ΔI 2 signal is generated by subtraction circuit 50 . This negativeΔI 2 signal is input into subtraction circuit 60 . Subtraction circuit 60 subtracts the negative ΔI 2 signal from VE/A, i.e. the output of error amplifier 42 , and the output 60 c, which is electrically connected to input 70 a of PWM 70 , is increased. In response, PWM 70 increases the pulse width of PWM 2 at output 14 b. The increase in pulse width of PWM 2 increases the current flowing through channel 18 b to a value closer to the average of all converter channel currents, as represented by V average .

In the embodiment shown, converter 10 includes four converter channels 18 a, 18 b, 18 c, 18 d, and control circuit 14 includes four control circuit channels, each including a respective subtraction circuit 48 , 50 , 52 , 54 , another respective subtraction circuit 58 , 60 , 62 , 64 , a respective compensation circuit G 1 , G 2 , G 3 , G 4 , a respective PWM amplifier 68 , 70 , 72 , 74 , and a respective feedback path 28 a, 28 b, 28 c, 28 d. However, it is to be understood that converter 10 can be configured to include any number of channels with control circuit 14 be configured with a corresponding number of control circuit channels.

In the embodiment shown, compensation circuits G 1 , G 2 , G 3 , G 4 each perform current loop compensation functions, such as, for example, gain or filter functions to shape the current feedback wave, or to prevent current loop instability. However, it is to be understood that it is not always necessary to incorporate compensation circuits into the present invention.

In the embodiment shown, signals V ISENSE1 , V ISENSE2 , V ISENSE3 , and V ISENSE4 are proportional to the current in each of feedback loops 28 a, 28 b, 28 c, 28 d, respectively. However, it is to be understood that the V ISENSE signals may be alternately configured such as being based upon or based partly upon the current carried by the feedback loops, rather than being strictly proportional thereto.

In the embodiment shown, circuits 48 , 50 , 52 , 54 , and circuits 58 , 60 , 62 , 64 are configured as subtraction circuits. However, it is to be understood that each of circuits 48 , 50 , 52 , 54 and circuits 58 , 60 , 62 , 64 could be alternatively configured, such as, for example, difference amplifiers, to produce an output signal representative of the difference between signals input into the circuits.

While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the present invention using the general principles described herein. Further, this application is intended to cover such departures from the present disclosure as come within the known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.