Electro-luminescence panel

This application claims the benefit of Korean Patent Application No. 2000-81417, filed on Dec. 23, 2000, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.

1. Field of the Invention

This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence panel that is capable of improving brightness.

2. Description of the Related Art

Recently, various flat panel display devices have been developed with reduced weight and bulk that are capable of eliminating the disadvantages associated with a cathode ray tube (CRT). Such flat panel display devices include liquid crystal displays (LCD), field emission displays (FED), plasma display panels (PDP) and electro-luminescence (EL) panels.

Studies have been made increasing the display quality of the flat panel display device and for providing the flat panel display with a large-scale screen. The EL panel in such display devices is a self-emission device. The EL panel excites a fluorescent material using carriers such as electrons and holes, to display a video image. The EL panel has advantages in that a low direct current driving voltage is possible and the response speed is fast.

Referring to FIG. 1, the conventional EL panel includes gate line pairs GL and /GL and data lines DL arranged on a glass substrate 10 in such a manner to cross each other, and pixel elements PE arranged at each crossing of the gate line pairs GL and /GL and the data lines DL. Each pixel element PE is driven when gate signals at the gate line pairs GL and /GL are enabled, to thereby generate light corresponding to the magnitude of pixel signals at the data lines DL.

In order to drive such pixel elements PE, a gate driver 12 is connected to the gate line pairs GL and /GL while a data driver 14 is connected to the data lines DL. The gate driver 12 drives the gate line pairs GL and /GL sequentially. The data driver 14 applies pixel signals to the pixels PE via the data lines DL.

Each of the pixel elements PE driven with the gate driver 12 and the data driver 14 in this manner includes an EL cell, that is, an organic light emitting diode OLED connected to a ground voltage line GND, and a cell driving circuit 16 for driving the EL cell OLED. The EL cell OLED emits light corresponding to an amount of current applied from the cell driving circuit 16 .

Referring to FIG. 2, the cell driving circuit 16 includes a first PMOS thin film transistor (TFT) MP 1 connected between first and second nodes N 1 and N 2 , and the EL cell OLED, a second PMOS TFT MP 2 connected between the second node N 2 and the EL cell OLED, and a capacitor C 1 connected between the first and second nodes N 1 and N 2 .

The capacitor C 1 charges a voltage of a pixel signal when the pixel signal is received from the data line DL and applies the charged pixel voltage to the gate electrode of the first PMOS TFT MP 1 . The first PMOS TFT MP 1 is turned on by the pixel voltage charged in the first capacitor C 1 , to thereby apply a supply voltage VDD from a voltage supply line VDDL, via the first node N 1 , to the EL cell OLED. At this time, a channel width of the first PMOS TFT MP 1 is varied depending on the voltage level of the pixel signal to control an amount of current applied to the EL cell OLED. Accordingly, the EL cell OLED generates light corresponding to the current amount applied from the first PMOS TFT MP 1 .

The second PMOS TFT MP 2 responds to a gate signal GLS, as shown in FIG. 3, applied from the gate line GL to selectively connect the second node N 2 to the EL cell OLED. More specifically, the second PMOS TFT MP 2 connects the second node N 2 to the EL cell OLED at a time interval when the gate signal GLS is enabled at a low logic, to thereby charge the pixel signal into the capacitor C 1 . In other words, the second PMOS TFT MP 2 forms a current path of the first capacitor C 1 at a time interval when the gate signal GLS at the gate line GL is enabled.

The capacitor C 1 charges a pixel signal at the enabling interval of the gate signal GLS and allows a voltage at the gate electrode of the first PMOS TFT MP 1 to go lower than a voltage at the drain electrode thereof by the voltage level of the charged pixel signal. Thus, the first PMOS TFT MP 1 controls its channel width depending on the voltage level of the pixel signal, to thereby determine the current amount flowing from the first node N 1 into the EL cell OLED.

The cell driving circuit 16 in FIG. 2 further includes a third PMOS TFT MP 3 responding to a gate signal GLS at the gate line GL, and a fourth PMOS TFT MP 4 responding to an inverted gate signal /GLS from the gate bar line /GL.

The third PMOS TFT MP 3 is turned on at a time interval when a low logic of the gate signal GLS is applied from the gate line GL, to thereby connect the capacitor C 1 connected to the first node N 1 and the drain electrode of the first PMOS TFT MP 1 to the data line DL. In other words, the third PMOS TFT MP 3 plays the role of sending a pixel signal at the data line DL to the first node N 1 in response to a low logic of gate signal GLS. As a result the third PMOS TFT MP 3 is turned on at a time interval when the gate signal GLS at the gate line GL remains at a low logic, to thereby charge the pixel signal into the capacitor C 1 connected between the first and second nodes N 1 and N 2 .

The fourth PMOS TFT MP 4 is turned on at a time interval when a low logic of the inverted gate signal /GLS from the gate inverting line /GL is applied to the gate electrode thereof, to thereby connect the first node N 1 to which the capacitor C 1 and the drain electrode of the first PMOS TFT MP 1 have been connected, to the voltage supply line VDDL. At a time interval when the fourth PMOS TFT MP 4 has been turned on, a supply voltage VDD at the voltage supply line VDDL is applied to the EL cell OLED, via the first node N 1 and the first PMOS TFT MP 1 . Thus, the EL cell OLED generates light corresponding to an amount of the voltage level of the pixel signal.

The EL panel as mentioned above receives the current required for generating light using the EL cell OLED from the PMOS TFT. Such a characteristic of the PMOS TFT is as shown in FIG. 4 .

Referring to FIG. 4, the characteristic of the PMOS TFT shows that a voltage VDS between the drain electrode and the source electrode and a drain current ID differs depending on a value of a gate voltage VG applied to the gate electrode. Particularly, in the EL panel, a control of the current is most important because light emission amount varies depending on an amount of the current.

A current applied to the EL cell OLED increases until it reaches a threshold voltage VTH of the PMOS TFT like portion ‘A’ indicated by the dotted lines in FIG. 4, with respect to a small variation of the voltage VDS between the drain electrode and the source electrode. As a result, there is a problem in that vertical and horizontal stripes occur at a video image displayed on the EL panel.

Accordingly, the present invention is directed to an electro-luminescence panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide an electro-luminescence panel that is capable of improving brightness.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages of the invention, an electro-luminescence panel according to one embodiment of the present invention includes a first electro-luminescence cell driving circuit arranged at a crossing of a first gate line and a data line to drive electro-luminescence cells; and a second electro-luminescence cell driving circuit arranged at each crossing of the gate lines other than the first gate line and the data lines to drive the electro-luminescence cells.

In the electro-luminescence panel, the first electro-luminescence cell driving circuit includes a power supply for supplying power to the electro-luminescence cells; a first PMOS thin film transistor connected between the power supply and the data line; a second PMOS thin film transistor connected between the power supply and the electro-luminescence cell; a third PMOS thin film transistor connected between the gate electrodes of the first and second PMOS thin film transistors to serve as a switch; and a capacitor connected between the gate electrode of the second PMOS thin film transistor and the power supply.

Current flowing at the second PMOS thin film transistor is controlled by a ratio of width (a portion in which a semiconductor layer overlaps with the gate line) to length (a distance between the source and the drain) of each of the first PMOS thin film transistor and the second PMOS thin film transistor.

In the electro-luminescence panel, the second electro-luminescence cell driving circuit includes a power supply for supplying power to the electro-luminescence cells; a fourth PMOS thin film transistor connected between the power supply and the electro-luminescence cell; a fifth PMOS thin film transistor connected between the data line and the gate electrodes of the fourth PMOS thin film transistor to serve as a switch; and a capacitor connected between the gate electrode of the fourth PMOS thin film transistor and the power supply.

A current flowing at the fourth PMOS thin film transistor is controlled by a ratio of width (a portion in which a semiconductor layer overlaps with the gate line) to length (a distance between the source and the drain) of each of the first PMOS thin film transistor and the fourth PMOS thin film transistor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a schematic block circuit diagram showing a configuration of a conventional electro-luminescence panel;

FIG. 2 is a detailed circuit diagram of the pixel element shown in FIG. 1;

FIG. 3 is a waveform diagram of a gate signal to be applied to the pixel element shown in FIG. 1;

FIG. 4 is a graph representing a characteristic of a thin film transistor;

FIG. 5 is a schematic block circuit diagram showing a configuration of an electro-luminescence panel according to an embodiment of the present invention;

FIG. 6 is a detailed circuit diagram of the pixel element shown in FIG. 5;

FIG. 7 is a circuit diagram of the first EL cell driving circuit PE 1 shown in FIG. 6; and

FIG. 8 is a circuit diagram of the second EL cell driving circuit PE 2 shown in FIG. 6 .

Reference will now be made in detail to an embodiment of the present invention, example of which is illustrated in the accompanying drawings.

Referring to FIG. 5, there is shown an electro-luminescence (EL) panel according to an embodiment of the present invention.

The EL panel includes gate lines GL and data lines DL arranged on a glass substrate 20 in such a manner to cross each other, first and second pixel elements PE 1 and PE 2 arranged at each crossing of the gate lines GL and the data lines DL. Each of the first and second pixel elements PE 1 and PE 2 is driven when gate signals at the gate lines GL are enabled, to thereby generates light corresponding to the magnitude of pixel signals at the data lines DL.

In order to drive such pixel elements PE 1 and PE 2 , a gate driver 22 is connected to the gate lines GL while a data driver 24 is connected to the data lines DL. The gate driver 22 drives the gate lines GL sequentially. The data driver 24 applies pixel signals to the first and second pixel elements PE 1 and PE 2 via the data lines DL.

Each of the first and second pixel elements PE 1 and PE 2 driven with the gate driver 22 and the data driver 24 in this manner includes a first EL cell driving circuit PE 1 arranged at a crossing of the first gate line GL and the data line DL to drive the EL panel, and a second EL cell driving circuit PE 2 arranged at each crossing of the gate lines GL 2 to GLn, shown in FIG. 6, other than the first gate line GL 1 and the data lines DL to drive the EL panel.

The first EL cell driving circuit PE 1 applies a forward current signal, varying a backward current amount at the data line DL to the EL cell OLED at a time interval when a gate signal at the gate line GL is enabled. To this end, as shown in FIG. 6, the first EL cell driving circuit PE 1 consists of an EL cell, that is, an organic light emitting diode OLED connected to a ground voltage line GND, and a compensation circuit 26 having three thin film transistors (TFTs) arranged at each crossing of the first gate line GL 1 and the data lines DL. The EL cell OLED emits light corresponding to an amount of current applied from the compensation circuit 26 .

The compensation circuit 26 includes first and second PMOS TFTs P 1 and P 2 connected to form a current mirror at the voltage supply line VDD, a third PMOS TFT P 3 connected between the gate electrodes of the first and second PMOS TFTs P 1 and P 2 to serve as a switch, and a capacitor CST 1 connected between the second PMOS TFT P 2 and the voltage supply line VDD.

The capacitor CST 1 charges a current signal at the data line DL when the voltage supply line VDD is connected to the data line DL and applies the charged current signal to the gate electrode of the second PMOS TFT P 2 . The second PMOS TFT P 2 is turned on by the current signal having been charged in the capacitor CST 1 to apply a supply voltage VDD at the voltage supply line VDD to the EL cell OLED. The third PMOS TFT P 3 plays a role to switch the first and second PMOS TFTs P 1 and P 2 . When the third PMOS TFT P 3 is turned on, the first and second PMOS TFTs P 1 and P 2 become a current mirror. Thus, as shown in FIG. 7, when the first PMOS TFT P 1 is turned on, a current ID with a constant magnitude flows at the first data line DL 1 via the first PMOS TFT P 1 and current being equal to an amount of the current ID flowing at the first data line DL 1 is applied to the EL cell OLED via the second PMOS TFT P 2 .

At this time, the current applied to the EL cell OLED is fed during a holding time resulting from the capacitor CST 1 . The current flowing at the first data line DL 1 and the current applied to the EL cell OLED are determined by a ratio of a width to a length of each of the first PMOS TFT P 1 and the second PMOS TFT P 2 . In other words, if a ratio of a width to a length of the first PMOS TFT P 1 is equal to that of the second PMOS TFT P 2 , then the same magnitude of current ID flows at the first data line DL 1 and the EL cell OLED. On the other hand, if a ratio of a width to a length between the first PMOS TFT P 1 and the second PMOS TFT T 2 is 1: K, then current flowing at the second PMOS TFT P 2 is larger, by a magnitude of K×current ID, than current flowing at the first PMOS TFT P 1 .

Accordingly, the first PMOS TFT P 1 and the second PMOS TFT P 2 can control current flowing at the second PMOS TFT P 2 without being influenced by a threshold voltage VTH. In other words, the current amount applied to the EL cell OLED can be controlled irrespective of the threshold voltage VTH.

As shown in FIG. 8, the second EL cell driving circuit PE 2 consists of an EL cell OLED connected to a ground voltage line GND, and a cell driving circuit 36 having two thin film transistors P 4 and P 5 arranged at each crossing of the gate lines GL 2 to GLn (not shown) other than the first gate line GL 1 and the data lines DL. The EL cell OLED emits light corresponding to an amount of current applied from the cell driving circuit 36 .

The cell driving circuit 36 applies a forward current signal which varies depending on the amount of backward current at the data line DL when a gate signal at the gate line GL is enabled to the EL cell OLED. To this end, the cell driving circuit 36 includes a fourth PMOS TFT P 4 connected between the EL cell OLED and the voltage supply line VDD, a fifth PMOS TFT PS connected between the gate electrode of the fourth PMOS TFT P 4 and the data lines DL to serve as a switch, and a capacitor CST 2 connected between the gate electrode of the fourth PMOS TFT P 4 and the voltage supply line VDD.

The capacitor CST 2 charges a current signal at the data line DL when the voltage supply line VDD is connected to the data line DL and applies the charged current signal to the gate electrode of the fourth PMOS TFT P 4 . The fourth PMOS TFT P 4 is turned on by the current signal having been charged in the capacitor CST 2 to apply a supply voltage VDD at the voltage supply line VDD to the EL cell OLED. The fifth PMOS TFT P 5 plays the role of switching the fourth PMOS TFT P 4 . When the fifth PMOS TFT P 5 is turned on, the fourth PMOS TFT P 4 forms a current mirror along with the first PMOS TFT P 1 of the above-mentioned first EL cell driving circuit PE 1 . Thus, the first PMOS TFT P 1 is turned on to allow a current ID with a constant magnitude to flow at the first data line DL via the first PMOS TFT P 1 , so that the current being equal to an amount of the current ID flowing at the first data line DL 1 is applied to the EL cell OLED via the fourth PMOS TFT P 4 .

At this time, the current applied to the EL cell OLED is fed during a holding time resulting from the capacitor CST 2 . The current flowing at the first data line DL 1 and the current applied to the EL cell OLED are determined by a ratio of a width to a length of each of the first PMOS TFT P 1 and the fourth PMOS TFT P 4 . In other words, if a ratio of a width to a length of the first PMOS TFT P 1 is equal to that of the fourth PMOS TFT P 4 , then the same magnitude of current ID flows at the first data line DL 1 and the EL cell OLED. On the other hand, if a ratio of a width to a length between the first PMOS TFT P 1 and the fourth PMOS TFT T 4 is 1: K, then the current flowing at the fourth PMOS TFT P 4 is larger, by a magnitude of the K×current ID, than the current flowing at the first PMOS TFT P 1 .

Accordingly, the first PMOS TFT P 1 and the fourth PMOS TFT P 4 can control current flowing at the fourth PMOS TFT P 4 without being influenced by a threshold voltage VTH. In other words, the current amount applied to the EL cell OLED can be controlled irrespective of the threshold voltage VTH.

As described above, the first PMOS TFT P 1 and the second PMOS TFT P 2 , taking a shape of a current mirror are provided at a crossing of the first gate line GL and the data line DL, so that the current amount applied to the EL cell OLED is not influenced by a threshold voltage of the TFT. Further, the fourth PMOS TFT P 4 forming a current mirror along with the first PMOS TFT P 1 is provided at the second to nth gate lines, GL 2 to GLn other than the first gate line, so that the current being equal to the current flowing at the data line DL via the first PMOS TFT P 1 is applied to the EL cell OLED via the fourth PMOS TFT P 4 .

Accordingly, it becomes possible to control an amount of current applied to the EL cell OELD by differentiating a ratio of width to length of each of the first and second PMOS TFTs P 1 and P 2 and the first and fourth PMOS TFTs P 1 and P 4 .

As described above, the electro-luminescence panel according to the present invention has advantages in that it can considerably improve an aperture ratio in comparison to the electro-luminescence panel which adopts a compensation circuit for each pixel by configuring a single compensation circuit for a single gate line. Also, it can improve a throughput and eliminate a stripe occurring at the pixel cell. Moreover, the electro-luminescence panel according to the present invention has reduced the number of TFTs from the conventional four-TFT structure into a two-TFT structure, thereby largely improving an aperture ratio.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.