Differential voltage controlled oscillator, and method therefor

1. Field of the Invention

The present invention relates to voltage controlled oscillators, and more particularly to differential voltage controlled oscillators.

2. Related Art

Voltage controlled oscillators are very important for applications such as processor clock generation and distribution, communications, system synchronization, and frequency synthesis. The trend among these applications demands higher frequency, lower power, higher density and lower jitter voltage controlled oscillators.

Current designs tend to achieve improvements in some of these parameters at the expense of others. For example, a conventional current starved ring oscillator typically has three or four levels of stacking, but extreme sensitivity to noise due to very high gain. Also, this type of conventional oscillator tends to be very sensitive to process and environmental variability, and to have high jitter. Further, some of these designs do not provide equally staggered phases. Conventional delay interpolating oscillators are capable of very low jitter due to low gain and low noise sensitivity, but they tend to be inherently limited in maximum frequency range, and are difficult to build in less than 4 levels. Conventional multiphase oscillators offer advantages by pipelining operations using equally spaced phases at lower frequencies, but control mechanisms in delay interpolators tend to introduce offsets from the ideal phase spacing. LC-based multiphase oscillators are capable of high frequency and extremely low jitter, but tend to be difficult to integrate and model and have very low tuning ranges.

Therefore a need exists for an improved voltage control oscillator.

The forgoing need is addressed, in a first form, by a voltage controlled oscillator that includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.

Objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates a three-stage, differential, voltage controlled oscillator, according to an embodiment.

FIG. 2A illustrates a pass gate for a pass gate pair of one of the control elements of FIG. 1, according to a first embodiment.

FIG. 2B illustrates a pass gate for a pass gate pair of one of the control elements of FIG. 1, according to a second embodiment.

FIG. 3 illustrates a typical delay cell for the oscillator of FIG. 1, according to a first embodiment.

FIG. 4 illustrates another typical delay cell for the oscillator of FIG. 1, according to a second embodiment.

The claims at the end of this application set out novel features which applicants believe are characteristic of the invention. The invention, a preferred mode of use, objectives and advantages, will best be understood by reference to the following detailed description of an illustrative embodiment read in conjunction with the accompanying drawings.

Referring now to FIG. 1, a three-stage, differential, voltage controlled oscillator 100 is illustrated, according to an embodiment. The oscillator 100 has a first differential delay cell 110 , a second differential delay cell 120 and a third differential delay cell 130 with connections among the cells so that the cells are connected in a ring. That is, there is a connection for differential outputs, out and out_bar, of the first delay cell 110 to the differential inputs, in and in_bar of the second delay cell 120 . Likewise, there is a connection for the differential outputs of the second delay cell 120 to the differential inputs of the third delay cell 130 , and there is a connection for the differential outputs of the third delay cell 130 to the differential inputs of the first delay cell 110 . The delay cells 110 , etc. logically invert their respective differential inputs.

The oscillator 100 also includes three non-inverting control elements, 140 , 150 and 160 . Each one of the control elements is coupled to “bypass” a set of two of the delay cells. (The term “bypass” will be further explained herein below.) Specifically, there are respective connections for differential inputs of control element 140 to the differential inputs of delay cell 110 and differential outputs of control element 140 to the differential outputs of delay cell 120 , so that control element 140 may be controlled to bypass delay cells 110 and 120 . Likewise, there are connections for the differential inputs of control element 150 to the differential inputs of delay cell 130 and the differential outputs of control element 150 to the differential outputs of delay cell 110 , permitting the control element 150 to bypass delay cells 130 and 110 . Finally, there are connections for the differential inputs of control element 160 to the differential inputs of delay cell 120 and the differential outputs of control element 160 to the differential outputs of delay cell 130 , permitting the control element 160 to bypass delay cells 120 and 130 .

In the embodiment, the control elements 140 , 150 and 160 each consist solely of a pair of pass gates. A typical one of the pass gates is labelled 170 in FIG. 1 . The pair of pass gates 170 of a control element 140 , etc. receive respective first and second voltages of a differential control voltage (not shown in FIG. 1) for the control element. Details of pass gate 170 are shown in FIG's 2 A and 2 B, according to alternative embodiments.

Referring now to FIG. 2A, a pass gate 170 is illustrated, as typical for a pass gate pair of one of the control elements 140 , 150 or 160 , according to a first embodiment. In this embodiment, the pass gate includes a P-channel field effect transistor (“PFET”) 205 and an N-channel field effect transistor (“NFET”) 210 pair. The PFET 205 has a first conducting electrode 206 , a second conducting electrode 207 and a gate 208 . Likewise, the NFET 210 has a first conducting electrode 211 , a second conducting electrode 212 and a gate 213 . The first conducting electrodes of each FET are coupled together, as are the second conducting electrodes. The gate 208 of PFET 205 is operable to receive the first voltage 209 of the control element's differential control voltage, while the gate 213 of NFET 210 is operable to receive the second voltage 214 of the control element's differential control voltage, which is reverse polarity with respect to the first voltage 209 . The corresponding second pass gate 170 (not shown) of the control element's pass gate pair is also operable to receive the voltages of the differential control voltage.

Referring now to FIG. 2B, a typical pass gate 170 is illustrated, according to a second embodiment. In this embodiment, the pass gate has only a single FET 220 , with a first conducting electrode 221 , a second conducting electrode 222 and a gate 223 . The gate 223 is operable to receive one of the control voltages for the pass gate's associated control element 140 , 150 or 160 . The corresponding second pass gate 170 (not shown ) of the control element's pass gate pair is also operable to receive the differential control voltages.

Referring now to FIG. 3, a delay cell 110 is shown, according to a first embodiment. NFET 320 and PFET 340 are connected in series. NFET 330 and PFET 350 are likewise connected in series, which is connected in parallel with the series NFET/PFET 320 / 340 . The source electrodes of the PFET's 340 and 350 are connected to Vdd. A current source 310 , circuitry for which is well known in the art, is interposed between ground and the source electrodes of NFET's 320 and 330 .

The delay cell 110 is operable to receive an input signal, in, on the gate of NFET 320 and to generate a complementary output, out, on the mutually coupled drain electrodes of NFET 320 and PFET 340 . Likewise, the delay cell 110 is operable to receive a complementary input signal, in_bar, on the gate of NFET 330 and to generate an output, out_bar, complementary to the in_bar signal, on the mutually coupled drain electrodes of NFET 330 and PFET 350 . The PFET's 340 and 350 are cross coupled to enhance switching speed. That is, the gate of the PFET 340 is coupled to the output, out_bar. Likewise, the gate of the PFET 350 is coupled to the output, out. To reduce supply voltage sensitivity, the inverters of the delay cell 110 have respective p-loads 360 and 370 . In the embodiment, the p-loads are diode connected PFET's, that is, the gates of the PFET's are connected to their own drains.

This embodiment of FIG. 3 is “fully” differential. That is, in normal operating mode, disturbances or noise that are common to both differential terminals are completely cancelled. To illlustrate this point, note that the sum of the currents that go through the left and right sides of the delay cell are constant, thanks to the current source. Thus an increase in the common-mode voltage on the inputs (or other disturbance that affects both sides similarly) does not result in an increase in the current through either side, and therefore does not result in a change in the oscillation frequency.

Referring now to FIG. 1 in connection also with FIG. 3, further aspects of operation of the oscillator 100 include the following. Differential signals propagate through the three delay cells 110 , etc. connected in a ring, and at least a portion of the signals are controlled to selectively bypass the delay cells. The term “bypass” is used with reference to the propagation path provided by the coupling of a control element from the input of one delay cell to the output of a second delay cell. It should, however, be understood that a control element does not, strictly speaking, entirely bypass its respective set of delay cells, and, correspondingly, the signals propagating around the ring do not entirely bypass the delay cells via the control elements. Rather, as the control voltage on each control element 140 , etc. is varied, oscillation frequency varies proportionally as the signal propagation varies through the respective control elements and delay cells. Thus, the delay through each of the control element's set of delay cells is effectively interpolated between the delay of the control element and its associated delay cells, e.g. control element 140 and associated delay cells 110 and 120 .

To acheive the proper interpolating effect, according to one design parameter of the embodiment, the transistors of delay cells and control elements are sized so that at the minimum control voltage level for a control element the propagation delay through the control element is no less than the delay through one delay cell, and at the maximum control voltage level the delay through the control element is no more than the delay through two delay cells. That is, outputs of respective delay cells and associated control elements, e.g., 110 and 150 , share common output nodes, e.g. “out” in FIG. 1 . Although the delay elements of FIG. 3 are amplifiers they do not necessarily overpower their associated control element in driving the voltage on the shared output nodes, due to relative sizes of their transistors, according to the embodiment. For example, transistors of the delay cell 110 are relatively small enough in comparison to certain of the transistors of the control element 150 so that the voltage driven at the “out” node is not unduely dominated by the delay cell 110 .

Referring now to FIG. 4, another, simpler delay cell 110 is shown, according to an alternative embodiment. In this delay cell 110 , NFET 410 and PFET 430 are connected in series. NFET 420 and PFET 440 are likewise connected in series and connected in parallel with NFET 410 /PFET 430 . The source electrodes of the PFET's 430 and 440 are connected to Vdd. The source electrodes of NFET's the 410 and 420 are connected to ground.

The delay cell 110 of FIG. 4 is operable to receive an input signal, in, on the gate of NFET 410 and to generate a complementary output, out, on the mutually coupled drain electrodes of NFET 410 and PFET 430 . Likewise, the delay cell 110 is operable to receive a complementary input signal, in_bar, on the gate of NFET 420 and to generate an output, out_bar, complementary to the in_bar signal, on the mutually coupled drain electrodes of NFET 420 and PFET 440 . As in the delay cell of FIG. 3, the PFET's of the FIG. 4 delay cell 110 are also cross coupled to enhance switching speed. That is, the gate of the PFET 430 is coupled to the output, out_bar, and the gate of the PFET 440 for the second inverter is coupled to the output, out. This delay cell 110 half FIG. 4 is based on SRAM design principles. The cell 110 features a differential configuration where the cross coupled gates of the PFET's work as loads that enhance switching speed and the gates of the NFET's provide both inputs.

The embodiments described herein above provide numerous advantages. The oscillator consumes very low power and has good insensitivity to voltage supply. It provides differential outputs, a feature which improves insensitivity to noise. High frequency is possible with the design due to relatively high swing potential and due to low parasitics resulting from reduced circuit complexity and size. The oscillator can provide multiple equally spaced phases for over sampling or pipeline applications, and has been shown to work in a low voltage environment (1.1 volts). Tuning range can be significantly large with monoticity. Gain and range can be externally controlled, which is important for limiting noise bandwidth and noise susceptibility, factors which often define jitter performance of an oscillator. Gain and range can be controlled during design, by modifying the size of the control pass gates. For example, a larger control device may result in a larger gain and range (up to a point where it results in too high parasitics).

With all the control elements 140 , etc. (FIG's 1 , 2 A and 2 B) controlled by a single differential control voltage, this tends to distribute interpolation uniformly around the ring of delay cells 110 , etc., (FIG's 1 , 3 and 4 ) which allows good duty cycle and phase linearity. That is, three substantially uniform differential signals may be picked off the outputs of the respective delay cells, and in this circumstance the three will tend to be equally spaced in phase with respect to one another. Alternatively, with the control elements 140 , etc. controlled by independent differential control voltages, the phases of the three differential signals can be varied, which is useful for phase tuning in some applications. Also, extremely simple interpolation elements are used in the disclosed embodiments, that is, control elements 140 , etc. consisting solely of passgates 170 . This results in very low parasitics, which tends to improve many performance parameters, including jitter. This arrangement with just passgates in the control elements results in non-inverting, i.e., monotonic, control elements. This also tends to result in faster signal propagation through the control elements, since it avoids the capacitance of inverter transistor gates in the propagation path.

The delay cell 110 of FIG. 3 is relatively simple, and thus contains low parasitics, so that low jitter and high gain are provided. Also, because it is not stacked high, the cell 110 works with relatively low supply voltage. Furthermore, while the cell 110 can provide full voltage swing, the cell 110 can also provide pseudo-sinusoidal, non-full voltage swing which tends to significantly reduce power consumption. (For example, an oscillator implemented with the cell 110 of FIG. 3 has been shown to consume 2 milliamperes with a 1.2 V supply in a 0.12 micron technology running at over 3 gigahertz. The entire oscillator in this implementation contained only eighteen transistors, and provided six equally spaced phases.) Delay cell transistor sizes are an important factor in acheiving this lower power, non-full swing operation. That is, relatively lower equivalent resistance p-loads and PFET's, reduced-current current sources, and generally lower gain for the delay cell tend to reduce swing. Of course overall operation of the oscillator is affected by the relative sizes of the delay cell and control element transistors, as previously described, so changes in delay cell transistors to reduce swing necessarily require corresponding changes in transistors for control elements.

The delay cell 110 of FIG. 4 can be applied to full swing applications, and due to its extraordinary simplicity has a small size and low parasitics. When correctly sized and buffered, a well-balanced, full swing, rectangular signal is provided by the cell. (An oscillator implemented with the delay cell 110 of FIG. 4 has been shown to consume around 5 milliamperes of worst-case current, with a 1.2 V supply in 0.12 micron technology running at over 3 gigahertz full swing.)

The description of the present embodiment has been presented for purposes of illustration, but is not intended to be exhaustive or to limit the invention to the form disclosed. Many additional aspects, modifications and variations are also contemplated and are intended to be encompassed within the scope of the following claims. For example, in the embodiment described in detail herein the oscillator has three stages. In other embodiments, the oscillator has more stages. Also, in FIG. 3 the current source is interposed between the NFET's and ground. In other embodiments the current source is interposed between the PFET's and the voltage source. In another variaion, to control gain and range after design, multiple input control devices can be put in parallel. By controlling the number of parallel control devices that are turned on or off, gain and range can be modified. For example, when four control pass gates in parallel are turned on, gain will generally be higher than when only one pass gate is on.