High voltage level shifter via capacitors

This invention relates to power switches, and more specifically, to an improved technique of providing level shifting required in a floating high side power switch in the half bridge configuration. The invention has specific application in power switches utilizing field effect transistor (FET) devices.

A half bridge configuration is utilized in connection with various power switch applications. Such a half bridge configuration typically involves an output signal interposed between two powered FET devices. An example of such prior art arrangement is shown in FIG. 1 .

In operation, the output signal V HB may fluctuate from nearly zero volts with respect to ground point 101 , up to nearly 400 volts, depending upon the parameters of the amplifying circuit and input power introduced into the circuit.

In order to properly operate transistor T 1 in its normal operating region, the gate voltage G 1 must be controlled with reference to the output signal V HB , not with respect to ground. Therefore, the power voltage F VDD should ideally be the equivalent of the voltage V DD of FIG. 1, except shifted by an amount substantially equal to V HB . Additionally, the gateway voltage G 1 for transistor T 1 should be equal to the appropriate voltage to turn on a transistor (e.g., G 2 ), shifted up by an amount substantially equal to V HB .

The circuitry for shifting the power source F VDD is known in the art and not critical to the present invention. Numerous circuits and related arrangements exist for generating such a voltage, and will not be discussed in detail herein. The particular circuitry used to generate the F VDD is not critical to the present invention.

In operation, a non-overlapping circuit 105 generates two non-overlapping pulses 106 and 107 . The first pulse 106 is transmitted via a driver 108 to the gate G 2 of a power transistor T 2 . Since the voltage is controlling transistor T 2 must be set with respect to a ground voltage, no level shifting is required.

Gate voltage G 1 controlling transistor T 1 must however, be set with respect to voltage V HB . Therefore, the remaining circuitry included within FIG. 1 is directed largely at voltage shifting the pulse 107 to provide the appropriate gate voltage G 1 adjusted by the dynamically moving signal V HB , which may be anywhere between zero and 400 volts.

In order to obtain the appropriate shift, two fixed current sources 112 and 114 are utilized. When the pulse generator 115 is on a rising edge, current source 114 is on and current source 112 is off. On a falling edge, the reverse happens, current source 112 being on and current source 114 being turned off.

In analysis of the remaining circuitry will show that power devices M 1 and M 2 each alternatively generate the required current through resistors M 9 and M 10 at the appropriate time in order to either set or reset, as appropriate, latch 116 . Therefore, upon rising edges latch 116 sets, and upon falling edges the latch resets. This causes the output of driver 117 to generate the appropriate gate voltage required to control transistor T 1 . Notably, since both the driver 117 and latch 116 are referenced to V HB , and since the supply voltage F VDD is shifted by V HB , everything operating with respect to transistor T 1 is with reference to V HB .

In summary, the circuitry of FIG. 1 operates by utilizing two current sources, a first of which induces a current sufficient to turn on a “set” transistor, and a second of which induces a current to turn on a “reset” transistor. By turning the appropriate current sources on or off at the appropriate times, a latch 116 is set or reset, and a driver 117 is controlled at a voltage that is relative not to ground but to a variable level signal V hb . This scenario appropriately drives the transistor T 1 .

A problem with the circuit of FIG. 1 is that it is lossy. The devices M 1 and M 2 and current sources 112 and 114 represent lossy devices, which waste relatively large amounts of power, particularly at high frequencies. Additionally, the current sources 112 and 114 are subject to the normal failure that is inherent in such active devices.

Therefore, it is desirable to provide a high power switching arrangement that can be utilized in a half bridge configuration while eliminating the high losses associated with active devices.

It is also desirable that such a circuit has a low manufacturing cost, and that it be more reliable than is presently achievable.

The above and other problems of the prior art are overcome in accordance with the present invention. Active devices utilized to effectuate the currents required to switch a latch are replaced with passive devices and small drivers. The drivers and passive devices have far less conduction losses than the active high voltage switches and current sources previously utilized.

In one preferred embodiment, the passive devices are capacitors, and the current is induced by a sudden change in voltage induced at one terminal of the capacitor. Since the capacitor has very low impedance at high frequencies, the sudden change in voltage induces a current large enough and for long enough to set or reset the latch as appropriate. Therefore, the capacitor, as a passive device, provides the required current required to set and reset a latch, and thus properly drive a transistor, rather than using an active device.

FIG. 1 depicts an amplifying circuit utilizing plural current sources in a prior art type of arrangement; and

FIG. 2 shows an exemplary embodiment of the invention wherein the current sources are replaced with passive devices, the passive devices being capacitors in the exemplary embodiment.

FIG. 2 shows an exemplary arrangement for implementing inventive techniques. Components of FIG. 2 are similar to those of FIG. 1 or labeled with the same numerals for clarity. The circuit of FIG. 2 also includes two capacitors 204 and 205 , and drivers 202 and 203 . Exemplary values of capacitors 204 and 205 would be 1 picofarad, for a circuit in which V HB was set at approximately 400 volts. The drivers 202 - 203 could be of a type commercially available as a discrete component or may be part of an integrated circuit that comprises the entire arrangement shown.

In operation, the rising edge of the pulse signal on line 107 is input to driver 202 and propagates through to inverting driver 203 . It can be appreciated that a rising edge will cause a current to be induced into capacitor 205 , whereas a falling edge will cause a current to be induced into capacitor 204 . Thus, the capacitors serve to induce the required current as a current source would do.

The current flows through resistor R 1 and causes the latch 116 to set its output, in a similar manner to that described with respect to the prior art. As a result of the latch 116 setting, driver 117 outputs a high signal into gate 1 of transistor T 1 . However, since driver 117 is referenced to the same point as V HB , the high input on gate G 1 of transistor T 1 is driven with a voltage relative to V HB , rather than relative to ground as is the case for transistor T 2 . Thus, the voltage of G 1 is V HB plus ten volts, where at least four volts is the required turn-on voltage to switch transistor T 1 on.

In a similar manner, capacitor 205 induces a current to flow through resistor R 2 . This current is sufficient to cause an appropriate voltage drop across R 2 and to thereby reset the latch 116 . Such a resetting causes a turning off of transistor T 1 by removal of the gate voltage G 1 .

In accordance with the invention then, a passive device is utilized to induce current sufficient to cause setting and resetting of a latch. The passive device utilized may include an inductor or other storage device, but in any event, does not require the pulse generation nor does the power of a switching transistor. Instead, the passive device inherently includes a time constant, which is selected sufficiently long can cause the latch to set or reset.

Selection of the devices 204 and 205 must be done in a manner sufficient to meet two separate requirements. First, the current must be sufficient to induce an appropriate voltage drop across R 1 or R 2 , as appropriate, in order to effectuate the setting or resetting of latch 116 .

Second, the time constant of the Resistor-Capacitor (R/C) circuit formed by capacitors 204 and 205 in conjunction with resistors R 1 and R 2 , respectively, must allow sufficient time for latch 116 to set or reset, as the case may be. In a typical application, the time required would be approximately forty nanoseconds. If the time constant is sufficiently long, and the capacitors 204 and 205 sufficiently large, then there will be a relatively constant current for the amount of time required to set or reset latch 116 as the case may be. Put another way, the time required to reset the latch 116 should be short relative to the time constant of the R/C circuit, so that the current does not drastically decay before the latch gets reset. This criteria is easy to meet, since a typical value of a time constant using a one picofarad capacitor would be eighty nonoseconds yet the latch can be reset in only forty nanoseconds.

Although the invention has been described with respect to capacitors, any passive device may be used, and the types of transistors may be substituted for the field effect transistors shown as T 1 and T 2 . Various other embodiments will be apparent to those of skill in the art and the above examples are for purposes of explanation only.