Capacitor of a semiconductor device and method of manufacturing the same

1. Field of the Invention

The present invention relates generally to a capacitor of a semiconductor device, and more particularly to, a capacitor of a semiconductor device capable of having high capacitance and reduced leakage current, and the method of manufacture thereof.

2. Description of the Related Art

As the memory cells of DRAM devices are increased, the areas allotted for each memory cell decreases. Therefore, memory cells are required to form a capacitor having a large capacitance to provide accurate data read while occupying a small area.

The capacitance of a capacitor is increased by using an insulating layer having a high dielectric constant as a dielectric layer or by enlarging the surface area of the capacitor. Recent highly-integrated DRAM semiconductor devices provide sufficient capacitance by using a TaON layer as the dielectric layer.

The conventional capacitor of a semiconductor device and the method of manufacture thereof will be described with reference to FIG. 1 .

FIG. 1 is a cross-sectional view showing a capacitor of a semiconductor device and the method of manufacture thereof according to the prior art.

Referring to FIG. 1, first, an interlayer insulating layer 3 is formed on a semiconductor substrate 1 having a transistor (not shown) thereon. The interlayer insulating layer is selectively removed, thereby forming a plug contact hole 5 to expose a part of the junction area of the transistor (not shown).

A doped polysilicon layer is deposited to be in contact with the exposed junction area (not shown) on the interlayer insulating layer 3 including the plug contact hole 5 . Then, a contact plug 7 is formed in the plug contact hole 5 by selectively removing the doped polysilicon layer.

Subsequently, a doped polysilicon layer is deposited and selectively patterned on the interlayer insulating layer 3 including the contact plug 7 to form a lower electrode 9 . The lower electrode 9 may be formed in a shape of a cylinder, pin or stack. The surface of lower electrode 9 is subjected to an in-situ plasma or HF cleaning process to prevent the formation of natural oxide layers.

TaON layers 11 are then formed on the surfaces of the lower electrode 9 and the interlayer insulating layer 3 as dielectric layers. The TaON layer 11 is formed by mutual surface chemical reaction between Ta chemical vapor, NH 3 gas and O 2 gas, wherein the Ta chemical vapor is obtained by evaporating a precursor such as Ta(OC 2 H 5 ) 5 .

The TaON layer 11 is crystallized by performing a thermal treatment at a predetermined temperature.

Finally, an upper electrode 13 is formed on the upper part of the TaON layer 11 , thereby completing a capacitor of a semiconductor device. Here, the upper electrode 13 is formed with metal materials such as TiN, TaN, W, WN, Wsi, Ru, RuO 2 , Ir, IrO 2 and Pt.

In the resultant capacitor, the TaON layer 11 has a high dielectric constant of approximately 20 to 25, and at the same time, a low oxidation reaction property since it comprises a stable combination of Ta—O—N. Therefore, it is possible to prevent the generation of natural oxide layers and increase of thickness of the dielectric layer in the following thermal treatment.

However, a capacitor and the method of manufacture according to the conventional art have several problems due to the fact that the lower electrode is formed with a doped polysilicon layer.

As is well-known, the doped polysilicon layer has an improved oxidation reaction property. Therefore, the surface of lower electrode is naturally oxidized during the thermal treatment to crystallize the TaON layer, thereby causing the generation of natural oxide layers.

The natural oxide layers comprise SiO 2 having a low dielectric constant, thereby increasing the thickness of dielectric layer and lowering the dielectric property. As a result, capacitance is decreased.

A method has been proposed to decrease the thickness of the dielectric layer T ox , to solve the problems. However, according to this method, leakage current is increased and performance of the capacitor is lowered.

The present invention solves the above problems and has as an object to provide a capacitor of a semiconductor device capable of having high capacitance and reduced leakage current.

In order to accomplish this object, one embodiment of the present invention comprises the steps of: providing a semiconductor substrate; forming a lower electrode on the semiconductor substrate; forming a Ta—O—Sn layer on the lower electrode; and forming an upper electrode on the Ta—O—Sn layer.

Another embodiment present invention comprises the steps of: providing a semiconductor substrate; forming a lower electrode on the semiconductor substrate; forming a nitride layer on the lower electrode; forming an oxide tin layer on the nitride layer; forming an amorphous TaON layer on the oxide tin layer; diffusing oxygen and tin in the oxide tin layer and the amorphous TaON layer by thermal treatment process, thereby changing the layers into a Ta—O—Sn layer; and forming an upper electrode on the Ta—O—Sn layer.

Yet another embodiment of the present invention comprises the steps of: providing a semiconductor substrate; forming an interlayer insulating layer on the semiconductor substrate and selectively patterning the interlayer insulating layer to form a first contact hole; forming a contact plug in the first contact hole; forming a cap oxide layer on the interlayer insulating layer including the contact plug; selectively removing the cap oxide layer to expose the contact plug to form a second contact hole; forming a conductive material layer on the cap oxide layer including the second contact hole; selectively removing the conductive material layer until the cap oxide layer is exposed to form a low electrode; removing the cap oxide layer and forming a nitride layer on the resultant structure; forming an oxide tin layer on the upper part of the nitride layer; forming an amorphous TaON layer on the upper part of the oxide tin layer; diffusing oxygen and tin in the amorphous TaON layer and oxide tin layer by thermal treatment process, thereby changing the layers into a Ta—O—Sn layer; and forming an upper electrode on the upper part of the Ta—O—Sn layer.

Still another embodiment of a capacitor of the semiconductor device according to the present invention comprises: a semiconductor substrate; a lower electrode formed on the semiconductor substrate; a crystallized TaON layer formed on the lower electrode; a Ta—O—Sn layer formed on the crystallized TaON layer; and an upper electrode formed on the Ta—O—Sn layer.

FIG. 1 is a cross-sectional view showing a capacitor of a conventional semiconductor device and the method of manufacture thereof.

FIGS. 2 to 5 are cross-sectional views showing a capacitor of a semiconductor device and the method of manufacture thereof according to the present invention.

A description of the preferred embodiment according to the present invention will be described in detail, with reference to the accompanying drawings.

FIGS. 2 to 5 are cross-sectional views showing a method of manufacturing a capacitor for a semiconductor device according to the present invention.

As shown in FIG. 2, an interlayer insulating layer 23 is formed on a semiconductor substrate 21 having a transistor (not shown) thereon and then selectively removed to form a plug contact hole 25 exposing a part of the junction area of the transistor (not shown).

A doped polysilicon layer is deposited to be in contact with the exposed junction area (not shown) on the interlayer insulating layer 23 including the plug contact hole 25 and then selectively removed to form a contact plug 27 in the plug contact hole 25 .

A cap oxide layer 29 is then deposited on the interlayer insulating layer 23 , including the contact plug 27 , and then selectively removed by a mask process using photolithography and by an etch process to form a lower electrode contact hole 31 exposing a predetermined part of the contact plug 27 and of the interlayer insulating layer 23 .

A doped polysilicon layer 33 is then deposited on the upper part of the cap oxide layer 29 , including on the lower electrode contact hole 31 .

Referring to FIG. 3, the doped polysilicon layer 33 is planarized in accordance with CMP until the upper part of the cap oxide layer 29 is exposed.

A lower electrode 33 a of the cylinder structure is formed by removing the cap oxide layer 29 in accordance with a wet etch process and cleaned using a HF or BOE solution.

Referring to FIG. 4, a nitride layer 35 is deposited on the resultant structure formed on the lower electrode 33 a . In order to prevent generation of a SiO 2 layer having a low dielectric constant between the TaON layer and the polysilicon of the lower electrode 33 a in the following thermal treatment, a nitride layer 35 is formed in a CVD chamber maintained at a temperature of from 300 to 450° C. with NH 3 gas supplied at a flow rate of from 50 to 150 sccm and plasma having RF power of from 50 to 300 W applied for 30 seconds to 1 minute. The nitride layer 35 may also be formed at a temperature of from 600 to 900° C. in an atmosphere of NH 3 gas using a Rapid Thermal Process (RTP) and furnace thermal treatment.

An oxide tin layer SnO 2 37 having low oxide generation Gibbs free energy is then deposited on the upper part of the nitride layer 35 . The oxide tin layer 37 is formed in a chamber maintaining a temperature of 300 to 500° C. and a pressure of from 0.2 to 1 torr by mutual surface chemical reaction between Sn chemical vapor and O 2 gas. The Sn chemical vapor is obtained by extracting a predetermined amount of Sn compound from SnEt 4 through a flow controller and evaporating the extracted Sn compound in an evaporator maintaining a temperature of 150 to 200° C. O 2 gas is injected into the chamber at a flow rate of 200 to 400 sccm through a flow controller.

An amorphous TaON layer 39 having a high dielectric constant is then deposited on the upper part of the oxide tin layer 37 . The TaON layer 39 is formed through a surface chemical reaction by supplying Ta chemical vapor and NH 3 gas into a chamber maintaining a temperature of from 350 to 450° C. at a flow rate of from 25 to 200 sccm. The Ta chemical vapor is obtained by extracting Ta compound from a precursor, Ta(OC 2 H 5 ) 5 , through a flow controller and evaporating the extracted Ta compound in an evaporator at a temperature of from 160 to 190° C.

Referring to FIG. 5, the resultant structure is subjected to thermal treatment, thereby forming a new Ta—O—Sn layer 41 . The Ta—O—Sn layer 41 is formed by diffusing O 2 and Sn in a second following thermal treatment for a double layer of TaON/SnO 2 . The thermal treatment is performed in a chamber at a temperature of from 600 to 800° C. and in an atmosphere of N 2 O and O 2 for 30 seconds to 1 hour by using a batch-type furnace and RTP.

The plasma thermal treatment may be performed at a temperature of 350 to 450° C. and at a pressure of 0.8 to 2 torr in-situ after the amorphous TaON layer 39 is deposited. The plasma thermal treatment is performed in a chamber supplied with O 2 gas and N 2 gas at a flow rate of from 50 to 200 sccm and applied at an RF power of from 30 to 300 w.

Subsequently, an upper electrode 43 is deposited on the upper part of the Ta—O—Sn layer 41 , thereby completing a capacitor of a semiconductor device. The upper electrode is formed with a metal material such as TiN, TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 or Pt. The upper electrode 43 may be formed as a stacked structure with a TiN layer and polysilicon layer. Here, the TiN layer is deposited by flowing NH 3 gas with a TiCl 4 base. The TiN chemical vapor is obtained by supplying TiCl 4 at a predetermined flow rate into an evaporator and then evaporating a predetermined amount at a temperature of 150 to 200° C. Then, NH 3 gas is supplied with a flow rate of from 10 to 1000 sccm into a chamber at a temperature of from 300 to 600° C. with the resultant chemical vapor and the TiN layer formed by a surface chemical reaction between them.

In the above preferred embodiment, the lower electrode is formed in the shape of a cylinder. However, it is also possible to form the lower electrode in a pin shape or in a stacked shape.

And, in the above preferred embodiment, the lower electrode is a polysilicon layer. However, a capacitor of a semiconductor device according to the present invention can be obtained by forming a Meta-stable Poly Silicon MPS structure with amorphous silicon layer.

As describe above, according to the present invention, an oxide tin layer SnO 2 , having a low oxide generation Gibbs free energy, is deposited before a TaON layer is deposited. A binary source of oxygen is obtained by the following thermal treatment, thereby improving the chemical composition rate of the TaON layer and leakage current properties thereof.

Moreover, O 2 and Sn are diffused by the following thermal treatment for a double layer of TaON/SnO 2 , thereby forming Ta—O—Sn. As a result, it is effective in improving the dielectric constant.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.