Inventor

Yao-Wen Chang

Inventor
Taipei, TW

Overview

120→
Patents
1996–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 120 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices18%
H10DInorganic electric semiconductor devices16%
G11CStatic stores11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10BElectronic memory devices9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10NElectric solid-state devices not otherwise provided for6%
G06FElectric digital data processing6%
H04LTransmission of digital information, e.g. telegraphic communication2%
C23CCoating metallic material2%
PatentTitleYear
D0909383Handheld computer device housing202110,879,266Semiconductor device and operating method thereof202010,796,954Semiconductor structure and method for forming the same202010,790,362Semiconductor structure and manufacturing method of the same202010,770,144Non-volatile memory and program method thereof202010,763,273Vertical GAA flash memory including two-transistor memory cells202010,741,262NAND flash operating techniques mitigating program disturbance202010,741,250Non-volatile memory device and driving method thereof202010,727,077Structure and method to expose memory cells with different sizes202010,727,399Top electrode cap structure for embedded memory202010,713,410Method for legalizing mixed-cell height standard cells of IC202010,658,318Film scheme for bumping202010,558,779Method of redistribution layer routing for 2.5-dimensional integrated circuit packages202010,505,103Top electrode cap structure for embedded memory201910,497,773Method to improve MIM device performance201910,468,587Semiconductor structure, electrode structure and method of forming the same201910,290,701MIM capacitor, semiconductor structure including MIM capacitors and method for manufacturing the same201910,276,779Top electrode cap structure for embedded memory201910,275,559Method for legalizing mixed-cell height standard cells of IC201910,176,999Semiconductor device having a multi-layer, metal-containing film201910,163,651Structure and method to expose memory cells with different sizes201810,115,896Semiconductor device and method of manufacturing the same201810,103,078Formation of getter layer for memory device201810,047,039Compounds, compositions and methods for treating tumors201810,043,705Memory device and method of forming thereof20189,978,457Method for operating memory array20189,956,191Composition of 5-nitrobenzoate derivatives as anti-metastatic agent that inhibits tumor cell-induced platelet aggregation20189,954,166Embedded memory device with a composite top electrode20189,940,424Systems and methods for minimum-implant-area aware detailed placement20189,928,334'Redistribution layer routing for integrated fan-out wafer-level chip-scale packages'20189,887,134'Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices'20189,858,995'Method for operating a memory device'20189,830,416Method for analog circuit placement20179,825,117'MIM/RRAM structure with improved capacitance and reduced leakage current'20179,818,885'Deposited material and method of formation'20179,761,799'Bottom electrode structure for improved electric field uniformity'20179,722,011'Film scheme for MIM device'20179,711,713'Semiconductor structure, electrode structure and method of forming the same'20179,685,389'Formation of getter layer for memory device'20179,633,920'Low damage passivation layer for III-V based devices'20179,625,520'Latch-up test device and method for testing wafer under test'20179,604,910'Composition of 5-nitrobenzoate derivatives as anti-metastatic agent that inhibits tumor cell-induced platelet aggregation'20179,558,988'Method for filling the trenches of shallow trench isolation (STI) regions'20179,543,375'MIM/RRAM structure with improved capacitance and reduced leakage current'20179,524,868'Deposited material and method of formation'20169,509,137'Electrostatic discharge protection device'20169,502,649'Bottom electrode structure for improved electric field uniformity'20169,466,375'Memory device and programming method thereof'20169,460,928'Method for manufacturing semiconductor devices'20169,450,183'Memory structure having top electrode with protrusion'20169,443,955'Semiconductor device and method for fabricating the same'20169,437,303'Programming method of memory array'20169,425,061'Buffer cap layer to improve MIM structure performance'20169,324,789'Memory device and method for fabricating the same'20169,281,195'Semiconductor structure'20169,257,642'Protective sidewall techniques for RRAM'20169,257,272'Deposited material and method of formation'20169,257,497'Metal-insulator-metal (MIM) capacitor techniques'20169,215,257'Terminal device and method for exchanging VoIP signaling'20159,208,892'Operation method of multi-level memory'20159,082,620'Semiconductor device'20158,952,484'Non-volatile memory having isolation structures in and above a substrate and manufacturing method thereof'20158,937,347'Non-volatile memory'20158,929,134'Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme'20158,902,880'Local terminal device and method for exchanging VoIP signaling'20148,875,083'Routing method for flip chip package and apparatus using the same'20148,836,005'Memory array'20148,817,436'Electrostatic discharge protection device'20148,776,000'Method of implementing timing engineering change order'20148,759,234'Deposited material and method of formation'20148,748,963'Non-volatile memory and manufacturing method thereof'20148,689,164'Method of analytical placement with weighted-average wirelength model'20148,675,322'Electrostatic discharge protection device'20148,661,388'Method of packing-based macro placement and semiconductor chip using the same'20148,644,081'Flash memory device and programming method thereof'20148,578,317'Routing method for flip chip package and apparatus using the same'20138,572,542'Clock-tree structure and method for synthesizing the same'20138,476,694'Memory cell, memory device and method for manufacturing memory cell'20138,462,773'Default gateway, terminal device, and method for exchanging VoIP signaling'20138,451,729'Embedded device and packet forwarding method'20138,411,506'Non-volatile memory and operating method of memory cell'20138,338,880'Flash memory'20128,340,141'Method of operating all-fiber-based ultra pulse laser system'20128,261,223'Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit'20128,259,492'Method of reading dual-bit memory cell'20128,248,937'Packet forwarding device and load balance method thereof'20128,228,727'Method for programming multi-level cell and memory apparatus'20128,213,469'Linear cavity of all-fiber-based ultra short pulse laser system'20128,203,879'Non-volatile memory and operation method thereof'20128,189,441'Method of recognizing track pitch of optical disk'20128,098,522'Non-volatile memory and operation method thereof'20128,093,665'Semiconductor device and method for fabricating the same'20128,072,803'Memory device and methods for fabricating and operating the same'20118,040,927'Ring or linear cavity of all-fiber-based ultra short pulse laser system and method of operating the same'20118,014,203'Memory device and methods for fabricating and operating the same'20118,004,890'Operation method of non-volatile memory'20117,898,873'Window enlargement by selective erase of non-volatile memory cells'20117,830,707'Method of reading dual-bit memory cell'20107,826,262'Operation method of nitride-based flash memory and method of reducing coupling interference'20107,808,037'High voltage device'20107,799,638'Method for forming a memory array'20107,707,536'V-shaped multilevel full-chip gridless routing'20107,692,968'Operation method of non-volatile memory and method of improving coupling interference from nitride-based memory'20107,603,640'Multilevel IC floorplanner'20097,486,086'Method for measuring intrinsic capacitance of a metal oxide semiconductor (MOS) device'20097,362,122'Method and circuit for extracting current-voltage characteristics of device'20086,834,263'NROM structure'20046,829,174'Method of narrowing threshold voltage distribution'20046,756,638'MOSFET structure with reduced junction capacitance'20046,683,352'Semiconductor device structure'20046,624,737'Voltage regulated circuit with well resistor divider'20036,549,029'Circuit and method for measuring capacitance'20036,486,028'Method of fabricating a nitride read-only-memory cell vertical structure'20026,481,860'Circular optical reflection apparatus'20026,465,849'CMOS structure having dynamic threshold voltage'20026,320,786'Method of controlling multi-state NROM'20016,285,483'Optical scanner'20016,091,516'Device for holding and moving a contact image sensor'20005,769,515'Optical scanners with an improved chassis locking means'19985,537,240'Brilliance control apparatus of light source in an optical scanner'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2002Based in Miaoli, TW· patent location history
2001–2020Patents assigned to MACRONIX INT CO LTD (52)· patent assignee history
2001–2020Based in Hsinchu, TW· patent location history
2009–2020Based in Taipei, TW· patent location history
2011–2015Patents assigned to CHANG YAO-WEN (28)· patent assignee history
2011–2015Patents assigned to LU TAO-CHENG (10)· patent assignee history
2011–2015Patents assigned to YANG I-CHEN (7)· patent assignee history
2014–2021Based in New Taipei, TW· patent location history
2015–2020Based in Zhubei City, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (35)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MACRONIX INT CO LTD522001–2020
TAIWAN SEMICONDUCTOR MFG CO LTD352016–2020
CHANG YAO-WENself282011–2015
LU TAO-CHENG102011–2015
YANG I-CHEN72011–2015
Locations
LocationPatentsSpan
Taipei, TW502009–2020
Hsinchu, TW472001–2020
Zhubei City, TW52015–2020
Miaoli, TW41996–2002
New Taipei, TW32014–2021