Inventor
Won Bae Bang
Inventor
Santa Clara, CA, US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
C23Cprimary
C23CCoating metallic material18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H01LSemiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H01JElectric discharge tubes or discharge lamps6%
Y10TTechnical subjects covered by former us classification4%
B22CFoundry moulding2%
B33YAdditive manufacturing, i.e. manufacturing of three-dimensional [3d] objects by additive deposition, additive agglomeration or additive layering, e.g. by 3d printing, stereolithography or selective laser sintering2%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds2%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients2%
PatentTitleYear
10,685,897Semiconductor package having routable encapsulated conductive substrate and method202010,468,343Method for fabricating semiconductor package and semiconductor package using the same201910,340,213Semiconductor device and manufacturing method thereof201910,224,218Method for fabricating semiconductor package having a multi-layer encapsulated conductive substrate and structure201910,177,117Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure201910,049,954Semiconductor package having routable encapsulated conductive substrate and method20189,978,695Semiconductor device including leadframe with a combination of leads and lands and method20189,922,919'Electronic package structure having insulated substrate with lands and conductive patterns'20189,881,864'Method for fabricating semiconductor package and semiconductor package using the same'20189,631,481'Semiconductor device including leadframe with a combination of leads and lands and method'20179,613,829'Method for fabricating semiconductor package and semiconductor package using the same'20179,552,999'Packaged electronic device having reduced parasitic effects and method'20179,508,631'Semiconductor device including leadframe with a combination of leads and lands and method'20169,275,939'Semiconductor device including leadframe with a combination of leads and lands and method'20168,648,450'Semiconductor device including leadframe with a combination of leads and lands'20147,841,582'Variable seal pressure slit valve doors for semiconductor manufacturing equipment'20107,806,383'Slit valve'20107,758,698'Dual top gas feed through distributor for high density plasma chamber'20107,754,282'Adjusting a spacing between a gas distribution member and a substrate support'20107,722,719'Gas baffle and distributor for semiconductor processing chamber'20107,456,116'Gap-fill depositions in the formation of silicon containing dielectric materials'20087,413,612'In situ substrate holder leveling method and apparatus'20087,335,609'Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials'20087,205,205'Ramp temperature techniques for improved mean wafer before clean'20077,204,888'Lift pin assembly for substrate processing'20077,192,486'Clog-resistant gas delivery system'20077,011,710'Concentration profile on demand gas delivery system (individual divert delivery system)'20066,793,965'Clog resistant injection valve'20046,629,559'Molds for casting with customized internal structure to collapse upon cooling and to facilitate control of heat transfer'20036,397,922'Molds for casting with customized internal structure to collapse upon cooling and to facilitate control of heat transfer'20026,379,492'Corrosion resistant coating'20026,346,481'Method of reducing pitting of a coated heater'20026,267,820'Clog resistant injection valve'20016,261,374'Clog resistant gas delivery system'20016,235,120'Coating for parts used in semiconductor processing chambers'20016,117,244'Deposition resistant lining for CVD chamber'20006,110,556'Lid assembly for a process chamber employing asymmetric flow geometries'20006,090,206'Throttle valve providing enhanced cleaning'20006,063,198'High pressure release device for semiconductor fabricating equipment'20005,948,958'Method and apparatus for verifying the calibration of semiconductor processing equipment'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2010Patents assigned to APPLIED MATERIALS INC (23)· patent assignee history
1999–2002Based in San Jose, CA, US· patent location history
2001–2010Based in Santa Clara, CA, US· patent location history
2002–2003Patents assigned to MASSACHUSETTS INST TECHNOLOGY (2)· patent assignee history
2014–2020Patents assigned to AMKOR TECHNOLOGY INC (15)· patent assignee history
2014Patents assigned to BAE JAE MIN (1)· patent assignee history
2016–2018Based in Seoul, KR· patent location history
2017–2020Based in Gyeonggi-do, KR· patent location history
2017–2019Based in Seongnam-si, KR· patent location history
2020Patents assigned to AMKOR TECH SINGAPORE HOLDING PTE LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 23 | 1999–2010 |
| AMKOR TECHNOLOGY INC | 15 | 2014–2020 |
| MASSACHUSETTS INST TECHNOLOGY | 2 | 2002–2003 |
| AMKOR TECH SINGAPORE HOLDING PTE LTD | 1 | 2020 |
| BAE JAE MIN | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 13 | 2001–2010 |
| San Jose, California, US | 8 | 1999–2002 |
| Gyeonggi-do, KR | 6 | 2017–2020 |
| Seongnam-si, KR | 4 | 2017–2019 |
| Seoul, KR | 4 | 2016–2018 |