Inventor
Uway Tseng
Inventor
Taichung, TW
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H10DInorganic electric semiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
H10BElectronic memory devices8%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation6%
PatentTitleYear
8,716,871'Big via structure'20148,680,635'CMOS image sensor big via bonding pad application for AICu process'20148,633,086'Power devices having reduced on-resistance and methods of their manufacture'20148,502,335'CMOS image sensor big via bonding pad application for AlCu Process'20138,344,471'CMOS image sensor big via bonding pad application for AICu process'20137,884,013'Dual damascene with via liner'20117,400,011'Non-volatile memory device having a nitride barrier to reduce the fast erase effect'20087,387,961'Dual damascene with via liner'20087,199,007'Non-volatile memory device having a nitride barrier to reduce the fast erase effect'20077,157,360'Memory device and method for forming a passivation layer thereon'20077,012,004'Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof'20066,960,506'Method of fabricating a memory device having a self-aligned contact'20056,916,736'Method of forming an intermetal dielectric layer'20056,867,466'Memory device and method for forming a passivation layer thereon'20056,746,968'Method of reducing charge loss for nonvolatile memory'20046,734,098'Method for fabricating cobalt salicide contact'20046,713,388'Method of fabricating a non-volatile memory device to eliminate charge loss'20046,562,682'Method for forming gate'20036,548,425'Method for fabricating an ONO layer of an NROM'20036,511,907'Method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process'20036,413,840'Method of gettering layer for improving chemical-mechanical polishing process in flash memory production and semiconductor structure thereof'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2008Patents assigned to MACRONIX INT CO LTD (14)· patent assignee history
2002–2011Based in Taichung, TW· patent location history
2003Based in Houli Shiang, TW· patent location history
2005–2008Based in Hsinchu, TW· patent location history
2008–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (7)· patent assignee history
2013–2014Patents assigned to TSENG UWAY (4)· patent assignee history
2013Patents assigned to LIN YU-TING (2)· patent assignee history
2013Patents assigned to WU LIN-JUNE (2)· patent assignee history
2013–2014Based in Chu-tung Town, TW· patent location history
2013–2014Based in Taizhong, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MACRONIX INT CO LTD | 14 | 2002–2008 |
| TAIWAN SEMICONDUCTOR MFG | 7 | 2008–2014 |
| TSENG UWAYself | 4 | 2013–2014 |
| LIN YU-TING | 2 | 2013 |
| WU LIN-JUNE | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 12 | 2002–2011 |
| Chu-tung Town, TW | 3 | 2013–2014 |
| Hsinchu, TW | 3 | 2005–2008 |
| Taizhong, TW | 2 | 2013–2014 |
| Houli Shiang, TW | 1 | 2003 |