Inventor
Thomas M. Maffitt
Inventor
Burlington, VT, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores72%
H03KPulse technique9%
H10BElectronic memory devices5%
G01KMeasuring temperature2%
G01RMeasuring electric variables2%
H01LSemiconductor devices2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H10DInorganic electric semiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,998,045Writing multiple levels in a phase change memory202110,943,658Writing multiple levels in a phase change memory202110,937,496Writing multiple levels in a phase change memory202110,762,959Writing multiple levels in a phase change memory202010,726,897Trimming MRAM sense amp with offset cancellation202010,726,898MRAM sense amplifier with second stage offset cancellation202010,692,576Writing multiple levels in a phase change memory202010,658,022High gain sense amplifier with offset cancellation for magnetoresistive random access memory202010,566,057Writing multiple levels in a phase change memory202010,535,403Writing multiple levels in a phase change memory202010,424,375Writing multiple levels in a phase change memory201910,037,802Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltage20189,911,492'Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period'20189,704,575'Content-addressable memory having multiple reference matchlines to reduce latency'20179,601,200'TCAM structures with reduced power supply noise'20179,583,192'Matchline precharge architecture for self-reference matchline sensing'20179,502,107'Writing multiple levels in a phase change memory'20169,384,792'Offset-cancelling self-reference STT-MRAM sense amplifier'20169,299,431'Writing multiple levels in a phase change memory using a write/read reference voltage ramping up over a write/read period'20168,520,458'Phase change memory cycle timer and method'20138,345,475'Non volatile cell and architecture with single bit random access read, program and erase'20138,300,489'Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump'20128,233,345'Phase change memory cycle timer and method'20127,882,455'Circuit and method using distributed phase change elements for across-chip temperature profiling'20117,778,065'Method and apparatus for implementing concurrent multiple level sensing operation for resistive memory devices'20107,660,152'Method and apparatus for implementing self-referencing read operation for PCRAM devices'20107,535,783'Apparatus and method for implementing precise sensing of PCRAM devices'20097,057,924'Precharging the write path of an MRAM device for fast write operation'20066,693,843'Wordline on and off voltage compensation circuit based on the array device threshold voltage'20046,580,650'DRAM word line voltage control to insure full cell writeback level'20036,522,154'Oxide tracking voltage reference'20036,496,037'Automatic off-chip driver adjustment based on load characteristics'20026,437,385'Integrated circuit capacitor'20026,369,671'Voltage controlled transmission line with real-time adaptive control'20026,255,899'Method and apparatus for increasing interchip communications rates'20016,177,818'Complementary depletion switch body stack off-chip driver'20016,014,046'Off chip driver (OCD) with variable drive capability for noise control'20005,995,440'Off-chip driver and receiver circuits for multiple voltage level DRAMs'19995,682,116'Off chip driver having slew rate control and differential voltage protection circuitry'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2021Patents assigned to IBM (36)· patent assignee history
1997–2021Based in Burlington, VT, US· patent location history
2012–2013Patents assigned to MAFFITT THOMAS M (4)· patent assignee history
2012–2013Patents assigned to GABRIC JOHN A (2)· patent assignee history
2012–2013Patents assigned to LAMOREY MARK C (2)· patent assignee history
2016–2017Patents assigned to GLOBALFOUNDRIES INC (4)· patent assignee history
2020Based in Butlington, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 36 | 1997–2021 |
| GLOBALFOUNDRIES INC | 4 | 2016–2017 |
| MAFFITT THOMAS Mself | 4 | 2012–2013 |
| GABRIC JOHN A | 2 | 2012–2013 |
| LAMOREY MARK C | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Burlington, VT, US | 37 | 1997–2021 |
| Butlington, VT, US | 2 | 2020 |