Inventor
Stephen Daley Arthur
Inventor
Glenville, NY, US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H01LSemiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
C30BSingle-crystal growth6%
Y10TTechnical subjects covered by former us classification5%
H03KPulse technique4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10HInorganic light-emitting semiconductor devices having potential barriers3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
11,069,772Techniques for fabricating planar charge balanced (CB) metal-oxide-semiconductor field-effect transistor (MOSFET) devices202111,056,586Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices202110,957,759Systems and methods for termination in silicon carbide charge balance power devices202110,903,330Tapered gate electrode for semiconductor devices202110,892,237Methods of fabricating high voltage semiconductor devices having improved electric field suppression202110,367,089Semiconductor device and method for reduced bias threshold instability20199,735,263'Transistor and switching system comprising silicon carbide and oxides of varying thicknesses, and method for providing the same'20179,576,868'Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices'20179,406,762'Semiconductor device with junction termination extension'20169,379,189'Method and system for transient voltage suppression'20169,257,283'Device having reduced bias temperature instability (BTI)'20169,123,798'Insulating gate field effect transistor device and method for providing the same'20159,006,027'Systems and methods for terminating junctions in wide bandgap semiconductor devices'20158,987,858'Method and system for transient voltage suppression'20158,815,721'Semiconductor device and method of manufacturing the same'20148,765,524'Method and system for transient voltage suppressors'20148,691,634'Optically triggered semiconductor device and method for making the same'20148,536,641'Semiconductor device'20138,530,902'System for transient voltage suppressors'20138,507,986'Silicon-carbide MOSFET cell structure and method for forming same'20138,466,007'Power semiconductor module and fabrication method'20138,377,812'SiC MOSFETs and self-aligned fabrication methods thereof'20138,377,756'Silicon-carbide MOSFET cell structure and method for forming same'20138,278,711'Semiconductor device and method of making the same'20128,216,370'Method for reducing defect concentration in crystals'20128,049,338'Power semiconductor module and fabrication method'20117,859,008'Crystalline composition, wafer, device, and associated method'20107,829,402'MOSFET devices and methods of making'20107,786,503'Gallium nitride crystals and wafers and method of making'20107,781,312'Silicon carbide devices and method of making'20107,760,005'Power electronic module including desaturation detection diode'20107,663,456'Micro-electromechanical system (MEMS) switch arrays'20107,638,815'Crystalline composition, wafer, and semi-conductor structure'20097,595,241'Method for fabricating silicon carbide vertical MOSFET devices'20097,527,742'Etchant, method of etching, laminate formed thereby, and device'20097,482,634'Monolithic array for solid state ultraviolet light emitters'20097,179,670'Flip-chip light emitting diode device without sub-mount'20077,175,704'Method for reducing defect concentrations in crystals'20077,078,731'Gallium nitride crystals and wafers and method of making'20067,002,156'Detection system including avalanche photodiode for use in harsh environments'20066,838,741'Avalanche photodiode for use in harsh environments'20055,880,513'Asymmetric snubber resistor'19995,654,226'Wafer bonding for power devices'19975,424,563'Apparatus and method for increasing breakdown voltage ruggedness in semiconductor devices'19955,041,896'Symmetrical blocking high voltage semiconductor device and method of fabrication'19914,939,101'Method of making direct bonded wafers having a void free interface'19904,927,772'Method of making high breakdown voltage semiconductor device'19904,814,283'Simple automated discretionary bonding of multiple parallel elements'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2021Patents assigned to GEN ELECTRIC (36)· patent assignee history
1989–1999Based in Scotia, NY, US· patent location history
1995–1999Patents assigned to HARRIS CORP (3)· patent assignee history
2005–2021Based in Glenville, NY, US· patent location history
2009–2012Patents assigned to MOMENTIVE PERFORMANCE MAT INC (5)· patent assignee history
2012–2019Patents assigned to ARTHUR STEPHEN DALEY (13)· patent assignee history
2012–2015Patents assigned to LOSEE PETER ALMERN (5)· patent assignee history
2013–2021Based in Niskayuna, NY, US· patent location history
2015Based in Schenectady, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GEN ELECTRIC | 36 | 1989–2021 |
| ARTHUR STEPHEN DALEYself | 13 | 2012–2019 |
| LOSEE PETER ALMERN | 5 | 2012–2015 |
| MOMENTIVE PERFORMANCE MAT INC | 5 | 2009–2012 |
| HARRIS CORP | 3 | 1995–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Glenville, New York, US | 36 | 2005–2021 |
| Scotia, New York, US | 7 | 1989–1999 |
| Niskayuna, New York, US | 4 | 2013–2021 |
| Schenectady, New York, US | 1 | 2015 |