Inventor

Solomon I. Beilin

Inventor

San Carlos, CA, US

Overview

1986–2005

Patent span

Electricity

Primary field (CPC H)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H05Kprimary

H05KPrinted circuits28%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%

Y10TTechnical subjects covered by former us classification12%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%

G02BOptical elements, systems or apparatus5%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%

H01GCapacitors2%

B24BMachines, devices, or processes for grinding or polishing1%

PatentTitleYear

6,866,741'Method for joining large substrates'2005 6,845,184'Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making'2005 6,785,447'Single and multilayer waveguides and fabrication process'2004 6,733,685'Methods of planarizing structures on wafers and substrates by polishing'2004 6,706,546'Optical reflective structures and method for making'2004 6,690,845'Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making'2004 6,684,007'Optical coupling structures and the fabrication processes'2004 6,662,443'Method of fabricating a substrate with a via connection'2003 6,611,635'Opto-electronic substrates with electrical and optical interconnections and methods for making'2003 6,579,474'Conductive composition'2003 6,572,780'Methods for fabricating flexible circuit structures'2003 6,544,430'Methods for detaching a layer from a substrate'2003 6,509,529'Isolated flip chip of BGA to minimize interconnect stress due to thermal mismatch'2003 6,444,921'Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like'2002 6,391,220'Methods for fabricating flexible circuit structures'2002 6,343,171'Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making'2002 6,326,555'Method and structure of z-connected laminated substrate for high density electronic packaging'2001 6,317,331'Wiring substrate with thermal insert'2001 6,299,053'Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch'2001 6,281,040'Methods for making circuit substrates and electrical assemblies'2001 6,239,485'Reduced cross-talk noise high density signal interposer with power and ground wrap'2001 6,226,171'Power conducting substrates with high-yield integrated substrate capacitor'2001 6,221,567'Method of patterning polyamic acid layers'2001 6,187,652'Method of fabrication of multiple-layer high density substrate'2001 6,146,241'Apparatus for uniform chemical mechanical polishing by intermittent lifting and reversible rotation'2000 6,106,923'Venting hole designs for multilayer conductor-dielectric structures'2000 6,102,710'Controlled impedance interposer substrate and method of making'2000 6,090,214'Cleaning method using ammonium persulphate to remove slurry particles from CMP substrates'2000 6,081,026'High density signal interposer with power and ground wrap'2000 6,054,761'Multi-layer circuit substrates and electrical assemblies having conductive composition connectors'2000 6,050,832'Chip and board stress relief interposer'2000 6,039,889'Process flows for formation of fine structure layer pairs on flexible films'2000 6,034,332'Power supply distribution structure for integrated circuit chip modules'2000 6,025,244'Self-aligned patterns by chemical-mechanical polishing particularly suited to the formation of MCM capacitors'2000 6,019,665'Controlled retention of slurry in chemical mechanical polishing'2000 5,942,373'Pattern or via structure formed through supplemental electron beam exposure and development to remove image residue'1999 5,930,890'Structure and fabrication procedure for a stable post'1999 5,916,453'Methods of planarizing structures on wafers and substrates by polishing'1999 5,891,354'Methods of etching through wafers and substrates with a composite etch stop layer'1999 5,872,696'Sputtered and anodized capacitors capable of withstanding exposure to high temperatures'1999 5,854,534'Controlled impedence interposer substrate'1998 5,789,140'Method of forming a pattern or via structure utilizing supplemental electron beam exposure and development to remove image residue'1998 5,778,529'Method of making a multichip module substrate'1998 5,773,889'Wire interconnect structures for connecting an integrated circuit to a substrate'1998 5,765,279'Methods of manufacturing power supply distribution structures for multichip modules'1998 5,746,903'Wet chemical processing techniques for plating high aspect ratio features'1998 5,722,162'Fabrication procedure for a stable post'1998 5,660,957'Electron-beam treatment procedure for patterned mask layers'1997 5,544,017'Multichip module substrate'1996 5,536,362'Wire interconnect structures for connecting an integrated circuit to a substrate'1996 5,474,458'Interconnect carriers having high-density vertical connectors and methods for making the same'1995 5,454,161'Through hole interconnect substrate fabrication process'1995 5,419,038'Method for fabricating thin-film interconnector'1995 5,406,446'Thin film capacitor'1995 5,376,586'Method of curing thin films of organic dielectric material'1994 5,334,804'Wire interconnect structures for connecting an integrated circuit to a substrate'1994 5,323,520'Process for fabricating a substrate with thin film capacitor'1994 4,620,916'Degradation retardants for electrophoretic display devices'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986Patents assigned to BEILIN SOLOMON I (1)· patent assignee history

1986Patents assigned to LIPTON LEWIS T (1)· patent assignee history

1986Based in Oakland, CA, US· patent location history

1994–2005Patents assigned to FUJITSU LTD (53)· patent assignee history

1994–2005Based in San Carlos, CA, US· patent location history

2001–2003Patents assigned to KULICKE & SOFFA HOLDINGS INC (3)· patent assignee history

2002Patents assigned to FUJITSU LTD INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FUJITSU LTD	53	1994–2005
KULICKE & SOFFA HOLDINGS INC	3	2001–2003
BEILIN SOLOMON Iself	1	1986
FUJITSU LTD INC	1	2002
LIPTON LEWIS T	1	1986

Locations

Location	Patents	Span
San Carlos, California, US	57	1994–2005
Oakland, California, US	1	1986