LexDanaLexDanabeta
Inventor

Shih-Wei Sun

Inventor
Taipei, TW

Overview

75→
Patents
1990–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 75 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10BElectronic memory devices14%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
C23CCoating metallic material2%
C09KMaterials for miscellaneous applications, not provided for elsewhere1%
H02JElectric power networks1%
PatentTitleYear
8,624,435'Power regulating apparatus'20148,062,536'High density plasma chemical vapor deposition process'20117,718,079'High density plasma chemical vapor deposition process'20107,615,434'CMOS device and fabricating method thereof'20097,514,014'High density plasma chemical vapor deposition process'20097,378,740'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit'20087,271,101'High density plasma chemical vapor deposition process'20077,078,346'High density plasma chemical vapor deposition process'20066,492,732'Interconnect structure with air gap compatible with unlanded vias'20026,492,256'Method for forming an interconnect structure with air gap compatible with unlanded vias'20026,362,101'Chemical mechanical polishing methods using low pH slurry mixtures'20026,350,672'Interconnect structure with gas dielectric compatible with unlanded vias'20026,265,780'Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit'20016,245,380'Method of forming bonding pad'20016,242,346'Metallization for uncovered contacts and vias'20016,242,296'Method of fabricating embedded DRAM'20016,238,972'Method for increasing capacitance'20016,214,671'Method of forming dual gate structure'20016,203,863'Method of gap filling'20016,200,629'Method of manufacturing multi-layer metal capacitor'20016,198,617'Multi-layer metal capacitor'20016,171,895'Fabrication of buried channel devices with shallow junction depth'20016,153,459'Method of fabricating dual gate structure of embedded DRAM'20006,153,466'Method for increasing capacitance'20006,143,601'Method of fabricating DRAM'20006,117,345'High density plasma chemical vapor deposition process'20006,114,200'Method of fabricating a dynamic random access memory device'20006,100,205'Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process'20006,027,996'Method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing'20006,025,264'Fabricating method of a barrier layer'20006,025,253'Differential poly-edge oxidation for stable SRAM cells'20006,020,258'Method for unlanded via etching using etch stop'20006,017,792'Process for fabricating a semiconductor device including a nonvolatile memory cell'20006,015,741'Method for forming self-aligned contact window'20006,013,555'Process for rounding an intersection between an HSG-SI grain and a polysilicon layer'20006,010,931'Planarization technique for DRAM cell capacitor electrode'20006,008,100'Metal-oxide semiconductor field effect transistor device fabrication process'19996,001,738'Method of forming salicide'19995,998,251'Process and structure for embedded DRAM'19995,976,931'Method for increasing capacitance'19995,968,610'Multi-step high density plasma chemical vapor deposition process'19995,960,299'Method of fabricating a shallow-trench isolation structure in integrated circuit'19995,936,286'Differential poly-edge oxidation for stable SRAM cells'19995,930,618'Method of Making High-K Dielectrics for embedded DRAMS'19995,920,779'Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits'19995,899,742'Manufacturing method for self-aligned local interconnects and contacts simultaneously'19995,885,894'Method of planarizing an inter-layer dielectric layer'19995,886,375'SRAM having improved soft-error immunity'19995,874,353'Method of forming a self-aligned silicide device'19995,869,368'Method to increase capacitance'19995,864,163'Fabrication of buried channel devices with shallow junction depth'19995,811,283'Silicon on insulator (SOI) dram cell structure and process'19985,801,094'Dual damascene process'19985,789,290'Polysilicon CMP process for high-density DRAM cell structures'19985,780,348'Method of making a self-aligned silicide component'19985,753,559'Method for growing hemispherical grain silicon'19985,744,841'Semiconductor device with ESD protection'19985,733,794'Process for forming a semiconductor device with ESD protection'19985,708,288'Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method'19985,670,387'Process for forming semiconductor-on-insulator device'19975,605,855'Process for fabricating a graded-channel MOS device'19975,552,332'Process for fabricating a MOSFET device having reduced reverse short channel effects'19965,545,574'Process for forming a semiconductor device having a metal-semiconductor compound'19965,496,764'Process for forming a semiconductor region adjacent to an insulating layer'19965,406,111'Protection device for an intergrated circuit and method of formation'19955,399,507'Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications'19955,381,040'Small geometry contact'19955,369,052'Method of forming dual field oxide isolation'19945,345,105'Structure for shielding conductors'19945,279,990'Method of making a small geometry contact using sidewall spacers'19945,262,353'Process for forming a structure which electrically shields conductors'19935,034,351'Process for forming a feature on a substrate without recessing the surface of the substrate'19914,994,410'Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process'19914,926,237'Device metallization, device and method'19904,897,364'Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2000Patents assigned to MOTOROLA INC (20)· patent assignee history
1990–2000Based in Austin, TX, US· patent location history
1998–2011Patents assigned to UNITED MICROELECTRONICS CORP (50)· patent assignee history
1998–2014Based in Taipei, TW· patent location history
1999–2011Based in Hsinchu, TW· patent location history
2011–2014Patents assigned to SUN SHIH-WEI (2)· patent assignee history
2011Patents assigned to LIU CHIH-CHIEN (1)· patent assignee history
2011Patents assigned to LUR WATER (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
UNITED MICROELECTRONICS CORP501998–2011
MOTOROLA INC201990–2000
SUN SHIH-WEIself22011–2014
LIU CHIH-CHIEN12011
LUR WATER12011
Locations
LocationPatentsSpan
Taipei, TW511998–2014
Austin, Texas, US201990–2000
Hsinchu, TW41999–2011