Inventor
Serafino Bueti
Inventor
Waterbury, VT, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
G01RMeasuring electric variables12%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
G01KMeasuring temperature4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G05DSystems for controlling or regulating non-electric variables4%
H04BTransmission4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
8,347,019'Structure for hardware assisted bus state transition circuit using content addressable memories'20138,291,357'On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations'20128,234,104'Simulation of digital circuits'20128,132,136'Dynamic critical path detector for digital logic circuit paths'20128,016,482'Method and systems of powering on integrated circuit'20117,941,772'Dynamic critical path detector for digital logic circuit paths'20117,865,789'System and method for system-on-chip interconnect verification'20117,823,107'Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design'20107,823,017'Structure for task based debugger (transaction-event-job-trigger)'20107,716,007'Design structures of powering on integrated circuit'20107,643,591'Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design'20107,594,140'Task based debugger (transaction-event-job-trigger)'20097,519,941'Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry'20097,511,548'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,483,806'Design structures, method and systems of powering on integrated circuit'20097,479,819'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,313,738'System and method for system-on-chip interconnect verification'20077,308,668'Apparatus and method for implementing an integrated circuit IP core library architecture'20077,275,011'Method and apparatus for monitoring integrated circuit temperature through deterministic path delays'20077,129,821'Communication systems and methods using microelectronics power distribution network'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2013Patents assigned to IBM (20)· patent assignee history
2006–2013Based in Waterbury, VT, US· patent location history
2012–2013Patents assigned to BUETI SERAFINO (4)· patent assignee history
2012–2013Patents assigned to WOODRUFF CHARLES S (3)· patent assignee history
2012Patents assigned to GOODNOW KENNETH J (2)· patent assignee history
2012Patents assigned to LEONARD TODD E (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 20 | 2006–2013 |
| BUETI SERAFINOself | 4 | 2012–2013 |
| WOODRUFF CHARLES S | 3 | 2012–2013 |
| GOODNOW KENNETH J | 2 | 2012 |
| LEONARD TODD E | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Waterbury, VT, US | 20 | 2006–2013 |