Inventor
Sebastian T. Ventrone
Inventor
South Burlington, VT, US
Overview
Patents· 214 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
H03KPulse technique10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
G11CStatic stores5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H01LSemiconductor devices5%
G01RMeasuring electric variables4%
H10DInorganic electric semiconductor devices3%
H04LTransmission of digital information, e.g. telegraphic communication2%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
11,121,097Active x-ray attack prevention device202111,101,010Sensing circuits for charge trap transistors202111,054,854System and method to drive logic circuit with non-deterministic clock edge variation202110,788,877Transition once multiplexer circuit202010,700,013IC wafer for identification of circuit dies after dicing202010,651,135Tamper detection for a chip package202010,511,143III-V lasers with on-chip integration201910,249,590Stacked dies using one or more interposers201910,197,730Optical through silicon via201910,083,891Memory having thermoelectric heat pump and related IC chip package and method20189,972,606Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding20189,871,020'Through silicon via sharing in a 3D integrated circuit'20189,741,695'Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding'20179,606,291'Multilevel waveguide structure'20179,600,901'Video tracker having digital signal processor'20179,588,293'MEMS based photonic devices and methods for forming'20179,496,981'System and method of masking electromagnetic interference (EMI) emissions of a circuit'20169,472,483'Integrated circuit cooling apparatus'20169,412,736'Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias'20169,310,576'Integrated circuit having redundant optical signal paths and method of creating same'20169,301,424'Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit'20169,299,590'Integrated micro-peltier cooling components in silicon-on-insulator (SOI) layers'20169,264,150'Reactive metal optical security device and methods of fabrication and use'20169,257,366'Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit'20169,201,806'Anticipatorily loading a page of memory'20159,184,112'Cooling apparatus for an integrated circuit'20159,058,903'Methods and circuits for disrupting integrated circuit function'20159,043,889'Method and apparatus for secure and reliable computing'20159,038,004'Automated integrated circuit design documentation'20158,988,140'Real-time adaptive voltage control of logic blocks'20158,823,491'Security-enhanced radio frequency object locator system, method and program storage device'20148,819,460'Dynamic energy management'20148,793,365'Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes'20148,756,549'Integrated circuit chip incorporating embedded thermal radiators for localized, on-demand, heating and a system and method for designing such an integrated circuit chip'20148,612,815'Asynchronous circuit with an at-speed built-in self-test (BIST) architecture'20138,575,964'Inactivity triggered self clocking logic family'20138,549,330'Dynamic energy management'20138,499,140'Dynamically adjusting pipelined data paths for improved power management'20138,424,071'Method and apparatus for secure and reliable computing'20138,341,428'System and method to protect computing systems'20128,302,037'Skewed double differential pair circuit for offset cancellation'20128,279,861'Real-time VoIP communications using n-Way selective language processing'20128,239,811'System and method for wireless and dynamic intra-process measurement of integrated circuit parameters'20128,239,791'Method of designing multi-state restore circuitry for restoring state to a power managed functional block'20128,200,987'Dynamic object-level code translation for improved performance of a computer processor'20128,188,765'Circuit and method for asynchronous pipeline processing with variable request signal delay'20128,174,329'Power management architecture and method of modulating oscillator frequency based on voltage supply'20128,122,273'Structure and method to optimize computational efficiency in low-power environments'20128,097,474'Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry'20128,086,832'Structure for dynamically adjusting pipelined data paths for improved power management'20118,077,534'Adaptive noise suppression using a noise look-up table'20118,055,925'Structure and method to optimize computational efficiency in low-power environments'20118,051,340'System and method for balancing delay of signal communication paths through well voltage adjustment'20118,037,337'Structures including circuits for noise reduction in digital systems'20118,016,482'Method and systems of powering on integrated circuit'20117,979,724'System and method for dynamically managing power consumption of integrated circuitry'20117,966,589'Structure for dynamic latch state saving device and protocol'20117,966,537'Digital reliability monitor having autonomic repair and notification capability'20117,937,560'Processor pipeline architecture logic state retention systems and methods'20117,932,774'Structure for intrinsic RC power distribution for noise filtering of analog supplies'20117,916,531'Memory elements and methods of using the same'20117,913,193'Determining relative amount of usage of data retaining device based on potential of charge storing device'20117,903,493'Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereof'20117,898,286'Critical path redundant logic for mitigation of hardware across chip variation'20117,895,459'Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly'20117,882,334'Processor pipeline architecture logic state retention systems and methods'20117,873,961'Supervisory operating system for running multiple child operating systems simultaneously and optimizing resource usage'20117,872,692'Structure for switching system for signal monitoring and switch-back control'20117,869,298'Determining relative amount of usage of data retaining device based on potential of charge storing device'20117,865,862'Design structure for dynamically selecting compiled instructions'20117,831,935'Method and architecture for power management of an electronic device'20107,823,002'Digital reliability monitor having autonomic repair and notification capability'20107,821,294'Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block'20107,823,107'Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design'20107,793,251'Method for increasing the manufacturing yield of programmable logic devices'20107,791,968'Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator'20107,773,159'Switching system for signal monitoring and switch-back control'20107,770,139'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20107,765,351'High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips'20107,761,690'Method, apparatus and computer program product for dynamically selecting compiled instructions'20107,755,420'Intrinsic RC power distribution for noise filtering of analog supplies'20107,750,670'System and method for dynamically executing a function in a programmable logic array'20107,752,355'Asynchronous packet based dual port link list header and data credit management structure'20107,743,270'Assigning clock arrival time for noise reduction'20107,732,949'System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly'20107,715,995'Design structure for measurement of power consumption within an integrated circuit'20107,716,007'Design structures of powering on integrated circuit'20107,644,327'System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA'20107,643,591'Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design'20107,633,819'Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator'20097,536,496'Method and apparatus for transmitting data in an integrated circuit'20097,511,548'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,495,492'Dynamic latch state saving device and protocol'20097,489,163'FPGA powerup to known functional state'20097,483,806'Design structures, method and systems of powering on integrated circuit'20097,479,819'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,477,541'Memory elements and methods of using the same'20097,478,280'Test system for integrated circuits'20097,469,395'Wiring optimizations for power'20087,463,083'Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers'20087,460,422'Determining history state of data based on state of partially depleted silicon-on-insulator'20087,459,936'Fast/slow state machine latch'20087,454,642'Method and architecture for power management of an electronic device'20087,449,942'Intrinsic RC power distribution for noise filtering of analog supplies'20087,429,877'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,417,453'System and method for dynamically executing a function in a programmable logic array'20087,418,580'Dynamic object-level code transaction for improved performance of a computer'20087,406,579'Selectively changeable line width memory'20087,403,039'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,404,114'System and method for balancing delay of signal communication paths through well voltage adjustment'20087,397,718'Determining relative amount of usage of data retaining device based on potential of charge storing device'20087,373,567'System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA'20087,362,138'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,358,823'Programmable capacitors and methods of using the same'20087,353,486'Data processing in digital systems'20087,350,108'Test system for integrated circuits'20087,346,875'Wiring optimizations for power'20087,331,021'Fast/slow state machine latch'20087,317,348'Noise reduction in digital systems'20087,304,493'FPGA powerup to known functional state'20077,286,770'Fiber optic transmission lines on an SOC'20077,287,177'Digital reliability monitor having autonomic repair and notification capability'20077,282,949'FPGA powerup to known functional state'20077,275,164'System and method for fencing any one of the plurality of voltage islands using a lookup table including AC and DC components for each functional block of the voltage islands'20077,257,788'Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits'20077,248,838'Wireless communication system within a system on a chip'20077,222,248'Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range'20077,218,135'Method and apparatus for reducing noise in a dynamic manner'20077,213,084'System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit'20077,212,987'System and method for planning a design project, coordinating project resources and tools and monitoring project progress'20077,146,392'Random number generator'20067,139,881'Semiconductor device comprising a plurality of memory structures'20067,135,907'Clock signal distribution utilizing differential sinusoidal signal pair'20067,134,104'Method of selectively building redundant logic structures to improve fault tolerance'20067,111,151'Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor'20067,107,469'Power down processing islands'20067,105,385'FPGA blocks with adjustable porosity pass thru'20067,103,320'Wireless communication system within a system on a chip'20067,091,743'Data acknowledgment using impedance mismatching'20067,085,913'Hub/router for communication between cores using cartesian coordinates'20067,085,993'System and method for correcting timing signals in integrated circuits'20067,080,344'Coding of FPGA and standard cell logic in a tiling structure'20067,071,757'Clock signal distribution utilizing differential sinusoidal signal pair'20067,065,733'Method for modifying the behavior of a state machine'20067,065,602'Circuit and method for pipelined insertion'20067,058,914'Automatic latch compression/reduction'20067,053,712'Method and apparatus for controlling common-mode output voltage in fully differential amplifiers'20067,000,214'Method for designing an integrated circuit having multiple voltage domains'20066,996,795'Data processing in digital systems'20066,985,004'Wiring optimizations for power'20066,978,234'Configurable real prototype hardware using cores and memory macros'20056,964,026'Method of updating a semiconductor design'20056,954,920'Method, program product, and design tool for automatic transmission line selection in application specific integrated circuits'20056,954,085'System and method for dynamically executing a function in a programmable logic array'20056,944,698'Method and apparatus for providing bus arbitrations in a data processing system'20056,934,656'Auto-linking of function logic state with testcase regression list'20056,880,074'In-line code suppression'20056,834,353'Method and apparatus for reducing power consumption of a processing integrated circuit'20046,825,711'Power reduction by stage in integrated circuit'20046,820,254'Method and system for optimizing code using an optimizing coprocessor'20046,794,706'Applications of space-charge-limited conduction induced current increase in nitride-oxide dielectric capacitors: voltage regulator for power supply system and others'20046,792,582'Concurrent logical and physical construction of voltage islands for mixed supply voltage designs'20046,720,673'Voltage island fencing'20046,711,719'Method and apparatus for reducing power consumption in VLSI circuit designs'20046,687,883'System and method for inserting leakage reduction control in logic circuits'20046,678,847'Real time function view system and method'20046,658,634'Logic power optimization algorithm'20036,636,995'Method of automatic latch insertion for testing application specific integrated circuits'20036,604,174'Performance based system and method for dynamic allocation of a unified multiport cache'20036,545,521'Low skew, power sequence independent CMOS receiver device'20036,535,016'Method and circuit for providing copy protection in an application-specific integrated circuit'20036,487,701'System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology'20026,479,974'Stacked voltage rails for low-voltage DC distribution'20026,477,654'Managing VT for reduced power using power setting commands in the instruction stream'20026,425,109'High level automatic core configuration'20026,425,092'Method and apparatus for preventing thermal failure in a semiconductor device through redundancy'20026,412,096'Method and apparatus for a hedge analysis technique for performance improvements of large scale integrated circuit logic design'20026,405,234'Full time operating system'20026,397,170'Simulation based power optimization'20026,345,362'Managing Vt for reduced power using a status table'20026,317,840'Control of multiple equivalent functional units for power reduction'20016,304,122'Low power LSSD flip flops and a flushable single clock splitter for flip flops'20016,282,144'Multi-ported memory with asynchronous and synchronous protocol'20016,275,968'Apparatus and method to reduce node toggling in semiconductor devices'20016,269,468'Split I/O circuit for performance optimization of digital circuits'20016,253,299'Virtual cache registers with selectable width for accommodating different precision data formats'20016,246,254'Method and circuit for providing copy protection in an application-specific integrated circuit'20016,237,101'Microprocessor including controller for reduced power consumption and method therefor'20016,237,132'Toggle based application specific core methodology'20016,205,518'Apparatus and method for reducing power consumption in a data processor executing an application code'20016,167,524'Apparatus and method for efficient battery utilization in portable personal computers'20006,141,351'Radio frequency bus for broadband microprocessor communications'20006,134,704'Integrated circuit macro apparatus'20006,119,241'Self regulating temperature/performance/voltage scheme for micros (X86)'20006,097,243'Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode'20006,081,135'Device and method to reduce power consumption in integrated semiconductor devices'20006,054,877'Low power multiplexer circuit'20006,026,471'Anticipating cache memory loader and method'20005,986,962'Internal shadow latch'19995,918,246'Apparatus and method for prefetching data based on information contained in a compiler generated program map'19995,902,044'Integrated hot spot detector for design, analysis, and control'19995,874,833'True/complement output bus for reduced simulataneous switching noise'19995,867,725'Concurrent multitasking in a uniprocessor'19995,835,504'Soft fuses using bist for cache self test'19985,832,284'Self regulating temperature/performance/voltage scheme for micros (X86)'19985,781,922'Page boundary caches'19985,761,719'On-chip memory map for processor cache macro'19985,594,895'Method and apparatus for switching between clock generators only when activity on a bus can be stopped'19975,564,042'Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions'19965,459,843'RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder'19955,440,689'Interprocessor communication system for direct processor to processor communication between internal general purpose registers transparent to the execution of processors thereof'19955,357,617'Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor'19945,300,831'Logic macro and protocol for reduced power consumption during idle state'19944,833,602'Signal generator using modulo means'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2017Patents assigned to IBM (196)· patent assignee history
1989–2021Based in South Burlington, VT, US· patent location history
1994–2016Patents assigned to VENTRONE SEBASTIAN T (21)· patent assignee history
1994–1999Based in Jericho, VT, US· patent location history
1999–2011Based in Burlington, VT, US· patent location history
2011–2013Patents assigned to NSAME PASCAL A (5)· patent assignee history
2011–2013Based in Essex Junction, VT, US· patent location history
2012–2016Patents assigned to GOODNOW KENNETH J (4)· patent assignee history
2016–2021Patents assigned to GLOBALFOUNDRIES INC (15)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 196 | 1989–2017 |
| VENTRONE SEBASTIAN Tself | 21 | 1994–2016 |
| GLOBALFOUNDRIES INC | 15 | 2016–2021 |
| NSAME PASCAL A | 5 | 2011–2013 |
| GOODNOW KENNETH J | 4 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 194 | 1989–2021 |
| Burlington, VT, US | 8 | 1999–2011 |
| Jericho, VT, US | 8 | 1994–1999 |
| Essex Junction, VT, US | 4 | 2011–2013 |