Inventor
Robert Hannon
Inventor
Wappingers Falls, NY, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices12%
H05KPrinted circuits7%
C04BLime, magnesia7%
Y10TTechnical subjects covered by former us classification6%
H10BElectronic memory devices5%
B22FWorking metallic powder3%
C22CAlloys3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,170,337Implant after through-silicon via (TSV) etch to getter mobile ions20199,406,561'Three dimensional integrated circuit integration using dielectric bonding first and through via formation last'20168,962,448'Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20158,921,198'Method and structure for forming a deep trench capacitor'20148,822,141'Front side wafer ID processing'20148,738,167'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,679,971'Metal-contamination-free through-substrate via structure'20148,664,081'Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier'20148,658,535'Optimized annular copper TSV'20148,629,553'3D integrated circuit device fabrication with precisely controllable substrate removal'20148,546,961'Alignment marks to enable 3D integration'20138,492,869'3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,492,878'Metal-contamination-free through-substrate via structure'20138,487,425'Optimized annular copper TSV'20138,455,270'3D multiple die stacking'20138,399,336'Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'20138,372,725'Structures and methods of forming pre fabricated deep trench capacitors for SOI substrates'20138,298,914'3D integrated circuit device fabrication using interface wafer as permanent carrier'20128,129,256'3D integrated circuit device fabrication with precisely controllable substrate removal'20128,076,756'Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures'20118,022,543'Underbump metallurgy for enhanced electromigration resistance'20117,955,955'Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures'20117,919,356'Method and structure to reduce cracking in flip chip underfill'20117,674,690'Inhibition of metal diffusion arising from laser dicing'20107,566,637'Method of inhibition of metal diffusion arising from laser dicing'20097,375,021'Method and structure for eliminating aluminum terminal pad material in semiconductor devices'20086,670,675'Deep trench body SOI contacts with epitaxial layer formation'20036,486,043'Method of forming dislocation filter in merged SOI and non-SOI chips'20026,353,246'Semiconductor device including dislocation in merged SOI/DRAM chips'20026,306,528'Method for the controlling of certain second phases in aluminum nitride'20016,297,127'Self-aligned deep trench isolation to shallow trench isolation'20016,261,876'Planar mixed SOI-bulk substrate for microelectronic applications'20016,200,373'Method for controlling of certain second phases in aluminum nitride'20016,096,580'Low programming voltage anti-fuse'20006,004,624'Method for the controlling of certain second phases in aluminum nitride'19995,932,043'Method for flat firing aluminum nitride/tungsten electronic modules'19995,904,868'Mounting and/or removing of components using optical fiber tools'19995,763,093'Aluminum nitride body having graded metallurgy'19985,742,021'High thermal conductivity substrate and the method of brazing a cap thereto'19985,682,589'Aluminum nitride body having graded metallurgy'19975,552,107'Aluminum nitride body having graded metallurgy'19965,552,232'Aluminum nitride body having graded metallurgy'19965,491,319'Laser ablation apparatus and method'19964,628,493'Sensor system with time division multiplexing telemetry'19864,509,170'Time division multiplex transmission of submultiplex sequences of signals from sections of a chain of data acquisition units'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–1986Based in Rochester, NY, US· patent location history
1996–2019Patents assigned to IBM (43)· patent assignee history
1996–2019Based in Wappingers Falls, NY, US· patent location history
2011–2016Patents assigned to HANNON ROBERT (16)· patent assignee history
2011–2016Patents assigned to FAROOQ MUKTA G (14)· patent assignee history
2012–2016Patents assigned to IYER SUBRAMANIAN S (12)· patent assignee history
2012–2015Patents assigned to KOESTER STEVEN J (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 43 | 1996–2019 |
| HANNON ROBERTself | 16 | 2011–2016 |
| FAROOQ MUKTA G | 14 | 2011–2016 |
| IYER SUBRAMANIAN S | 12 | 2012–2016 |
| KOESTER STEVEN J | 8 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 43 | 1996–2019 |
| Rochester, New York, US | 2 | 1985–1986 |