Inventor
Nagaraj Savithri
Inventor
Dallas, TX, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing55%
G01RMeasuring electric variables15%
H03KPulse technique9%
G11CStatic stores6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
Y02PClimate change mitigation technologies in the production or processing of goods6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
PatentTitleYear
10,289,784Determination of clock path delays and implementation of a circuit design201910,162,916Timing verification in a programmable circuit design using variation factors20189,915,696'Area-efficient performance monitors for adaptive voltage scaling'20189,885,750'Speed model tuning for programmable integrated circuits with consideration of device yield, simulated frequency of operation, and speed of device components'20189,639,640'Generation of delay values for a simulation model of circuit elements in a clock network'20179,501,604'Testing critical paths of a circuit design'20169,405,871'Determination of path delays in circuit designs'20169,372,948'Interconnect speed model characterization in programmable integrated circuits'20169,065,446'Generating delay values for different contexts of a circuit'20158,112,737'Contact resistance and capacitance for semiconductor devices'20128,013,635'Multi-mode circuit and a method for preventing degradation in the multi-mode circuit'20117,694,269'Method for positioning sub-resolution assist features'20107,441,218'Contact resistance and capacitance for semiconductor devices'20087,318,208'Method for circuit sensitivity driven parasitic extraction'20087,129,696'Method for capacitance measurement in silicon'20067,109,738'Method for modeling inductive effects on circuit performance'20066,732,339'Cell-based noise characterization and evaluation'20046,700,399'High density parasitic measurement structure'20046,499,131'Method for verification of crosstalk noise in a CMOS design'20026,493,853'Cell-based noise characterization and evaluation'20026,378,109'Method of simulation for gate oxide integrity check on an entire IC'20026,363,516'Method for hierarchical parasitic extraction of a CMOS design'20026,253,359'Method for analyzing circuit delays caused by capacitive coupling in digital circuits'20016,038,383'Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2012Patents assigned to TEXAS INSTRUMENTS INC (15)· patent assignee history
2000–2012Based in Dallas, TX, US· patent location history
2011–2019Based in Richardson, TX, US· patent location history
2012Patents assigned to GURUMURTHY GIRISHANKAR (1)· patent assignee history
2012Patents assigned to SAVITHRI NAGARAJ N (1)· patent assignee history
2012Patents assigned to SHAH DHARIN NAYESHBHAI (1)· patent assignee history
2015–2019Patents assigned to XILINX INC (9)· patent assignee history
2015–2018Based in Plano, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 15 | 2000–2012 |
| XILINX INC | 9 | 2015–2019 |
| GURUMURTHY GIRISHANKAR | 1 | 2012 |
| SAVITHRI NAGARAJ Nself | 1 | 2012 |
| SHAH DHARIN NAYESHBHAI | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dallas, Texas, US | 14 | 2000–2012 |
| Plano, Texas, US | 7 | 2015–2018 |
| Richardson, Texas, US | 3 | 2011–2019 |