Inventor
Jayanthi Pallinti
Inventor
Santa Clara, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1052%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
B24BMachines, devices, or processes for grinding or polishing7%
B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool3%
C25FProcesses for the electrolytic removal of materials from objects3%
H05KPrinted circuits3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
8,552,560'Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing'20138,076,779'Reduction of macro level stresses in copper/low-K wafers'20117,531,442'Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing'20097,205,673'Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing'20076,951,808'Metal planarization system'20056,838,379'PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER'20056,752,916'Electrochemical planarization end point detection'20046,713,394'Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures'20046,607,967'Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate'20036,586,326'Metal planarization system'20036,555,475'Arrangement and method for polishing a surface of a semiconductor wafer'20036,503,828'Process for selective polishing of metal-filled trenches of integrated circuit structures'20036,489,242'Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures'20026,439,981'Arrangement and method for polishing a surface of a semiconductor wafer'20026,424,019'Shallow trench isolation chemical-mechanical polishing process'20026,417,093'Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing'20026,391,768'Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure'20026,372,524'Method for CMP endpoint detection'20026,060,370'Method for shallow trench isolations with chemical-mechanical polishing'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2007Patents assigned to LSI LOGIC CORP (16)· patent assignee history
2000–2013Based in Santa Clara, CA, US· patent location history
2005Based in Gresham, OR, US· patent location history
2009–2013Patents assigned to LSI CORP (3)· patent assignee history
2011–2013Patents assigned to BHATT HEMANSHU (2)· patent assignee history
2011–2013Patents assigned to KAO CHIYI (2)· patent assignee history
2011–2013Patents assigned to PALLINTI JAYANTHI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 16 | 2000–2007 |
| LSI CORP | 3 | 2009–2013 |
| BHATT HEMANSHU | 2 | 2011–2013 |
| KAO CHIYI | 2 | 2011–2013 |
| PALLINTI JAYANTHIself | 2 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 18 | 2000–2013 |
| Gresham, OR, US | 1 | 2005 |