Inventor
Jan Edward Vandemeer
Inventor
Kernersville, NC, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
B81Cprimary
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems19%
B81BMicrostructural devices or systems, e.g. micromechanical devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H01LSemiconductor devices14%
H10DInorganic electric semiconductor devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G01PMeasuring linear or angular speed, acceleration, deceleration, or shock7%
H01HElectric switches2%
H05KPrinted circuits2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,804,179Wafer-level package with enhanced performance202010,759,660Method for processing product wafers using carrier substrates202010,679,918Wafer-level package with enhanced performance202010,636,720Wafer-level package with enhanced performance202010,600,711Wafer-level package with enhanced performance202010,529,639Wafer-level package with enhanced performance202010,486,963Wafer-level package with enhanced performance201910,490,476Wafer-level package with enhanced performance201910,486,965Wafer-level package with enhanced performance201910,442,684Wafer-level package with enhanced performance201910,442,687Wafer-level package with enhanced performance201910,407,302Wafer-level package with enhanced performance201910,377,627Wafer-level package with enhanced performance201910,364,146Wafer-level package with enhanced performance201910,239,751Wafer-level package with enhanced performance201910,227,231Wafer-level package with enhanced performance201910,196,260Wafer-level package with enhanced performance201910,160,643Wafer-level package with enhanced performance201810,155,658Wafer-level package with enhanced performance201810,109,550Wafer-level package with enhanced performance201810,038,055Substrate structure with embedded layer for post-processing silicon handle elimination20189,978,838Substrate structure with embedded layer for post-processing silicon handle elimination20189,947,745Substrate structure with embedded layer for post-processing silicon handle elimination20189,806,192'Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate'20179,688,529'Glass wafer assembly'20178,314,467'Thermally tolerant electromechanical actuators'20128,094,980'Proof-mass with supporting structure on integrated circuit-MEMS platform and method of fabricating the same'20127,640,805'Proof-mass with supporting structure on integrated circuit-MEMS platform'20107,000,473'MEM structure having reduced spring stiction'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006Patents assigned to FREESCALE SEMICONDUCTOR INC (1)· patent assignee history
2006–2020Based in Mesa, AZ, US· patent location history
2010–2012Patents assigned to AKUSTICA INC (2)· patent assignee history
2010–2012Based in Bethel Park, PA, US· patent location history
2012–2020Patents assigned to RF MICRO DEVICES INC (4)· patent assignee history
2012Patents assigned to DIAMOND BRETT M (1)· patent assignee history
2017–2020Patents assigned to QORVO US INC (8)· patent assignee history
2017–2020Based in Kernersville, NC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QORVO US INC | 8 | 2017–2020 |
| RF MICRO DEVICES INC | 4 | 2012–2020 |
| AKUSTICA INC | 2 | 2010–2012 |
| DIAMOND BRETT M | 1 | 2012 |
| FREESCALE SEMICONDUCTOR INC | 1 | 2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kernersville, NC, US | 23 | 2017–2020 |
| Mesa, AZ, US | 4 | 2006–2020 |
| Bethel Park, Pennsylvania, US | 2 | 2010–2012 |