Inventor
Curtis C. Wollbrink
Inventor
Rochester, MN, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing80%
H04LTransmission of digital information, e.g. telegraphic communication14%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
PatentTitleYear
10,761,995Integrated circuit and data processing system having a configurable cache directory for an accelerator202010,554,347Low latency corrupt data tagging on a cross-chip link202010,396,944Low latency corrupt data tagging on a cross-chip link201910,216,653Pre-transmission data reordering for a serial interface20199,684,618'Peripheral component interconnect express (PCIe) ping in a switch-based environment'20179,563,591'Peripheral component interconnect express (PCIe) ping in a switch-based environment'20179,292,460'Versatile lane configuration using a PCIe PIE-8 interface'20169,292,462'Broadcast for a distributed switch network'20169,122,604'External settings that reconfigure the error handling behavior of a distributed PCIe switch'20159,087,162'Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch'20159,043,526'Versatile lane configuration using a PCIe PIe-8 interface'20158,949,499'Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch'20158,898,359'Bandwidth limiting on generated PCIe packets from debug source'20148,793,539'External settings that reconfigure the error handling behavior of a distributed PCIe switch'20148,706,938'Bandwidth limiting on generated PCIE packets from debug source'20148,683,107'Memory mapped input/output bus address range translation'20148,650,349'Memory mapped input/output bus address range translation for virtual bridges'20148,606,984'Hierarchical to physical bus translation'20138,429,323'Memory mapped input/output bus address range translation'20138,364,879'Hierarchical to physical memory mapped input/output translation'20138,327,055'Translating a requester identifier to a chip identifier'20128,316,169'Physical to hierarchical bus translation'20128,271,710'Moving ownership of a device between compute elements'20128,266,331'Transmitting retry request associated with non-posted command via response credit channel'20127,660,917'System and method of implementing multiple internal virtual channels based on a single external virtual channel'20107,496,707'Dynamically scalable queues for performance driven PCI express memory traffic'20096,968,418'Data forwarding by host/PCI-X bridges with buffered packet size determined using system information'20056,581,129'Intelligent PCI/PCI-X host bridge'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2020Patents assigned to IBM (28)· patent assignee history
2003–2020Based in Rochester, MN, US· patent location history
2012–2015Patents assigned to WOLLBRINK CURTIS C (12)· patent assignee history
2012–2014Patents assigned to THURBER STEVEN M (7)· patent assignee history
2012–2013Patents assigned to ENGEBRETSEN DAVID R (6)· patent assignee history
2012–2015Patents assigned to FREKING RONALD E (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 28 | 2003–2020 |
| WOLLBRINK CURTIS Cself | 12 | 2012–2015 |
| THURBER STEVEN M | 7 | 2012–2014 |
| ENGEBRETSEN DAVID R | 6 | 2012–2013 |
| FREKING RONALD E | 6 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 28 | 2003–2020 |