Inventor
Trent S. Uehling
Inventor
New Braunfels, TX, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H05KPrinted circuits4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
B23KSoldering or unsoldering2%
C23CCoating metallic material2%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application2%
G01RMeasuring electric variables2%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
11,018,024Method of fabricating embedded traces202110,037,970Multiple interconnections between die20189,935,079Laser sintered interconnections between die20189,703,056'Copper tube interconnect'20179,659,831'Methods and structures for detecting low strength in an interlayer dielectric structure'20179,548,256'Heat spreader and method for forming'20179,496,212'Substrate core via structure'20169,466,544'Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device'20169,385,064'Heat sink having a through-opening'20169,373,539'Collapsible probe tower device and method of forming thereof'20169,324,667'Semiconductor devices with compliant interconnects'20169,093,515'Wire bonding capillary with working tip protrusion'20159,070,657'Heat conductive substrate for integrated circuit package'20158,994,190'Low-temperature flip chip die attach'20158,895,409'Semiconductor wafer plating bus and method for forming'20148,766,453'Packaged integrated circuit having large solder pads and method for forming'20148,704,370'Semiconductor package structure having an air gap and method for forming'20148,519,513'Semiconductor wafer plating bus'20138,368,172'Fused buss for plating features on a semiconductor die'20138,349,666'Fused buss for plating features on a semiconductor die'20138,314,026'Anchored conductive via and method for forming'20128,008,786'Dynamic pad size to reduce solder fatigue'20117,772,104'Dynamic pad size to reduce solder fatigue'20107,276,435'Die level metal density gradient for improved flip chip package reliability'20077,129,566'Scribe street structure for backend interconnect semiconductor wafer integration'20066,951,801'Metal reduction in wafer scribe area'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (23)· patent assignee history
2005–2021Based in New Braunfels, TX, US· patent location history
2012–2017Patents assigned to UEHLING TRENT S (12)· patent assignee history
2013Patents assigned to HESS KEVIN J (2)· patent assignee history
2014–2016Patents assigned to WILKERSON BRETT P (3)· patent assignee history
2017–2021Patents assigned to NXP USA INC (6)· patent assignee history
2017–2018Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 23 | 2005–2018 |
| UEHLING TRENT Sself | 12 | 2012–2017 |
| NXP USA INC | 6 | 2017–2021 |
| WILKERSON BRETT P | 3 | 2014–2016 |
| HESS KEVIN J | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Braunfels, Texas, US | 24 | 2005–2021 |
| Austin, Texas, US | 2 | 2017–2018 |