Inventor
Adi Srinivasan
Inventor
Fremont, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
H03KPulse technique31%
G11CStatic stores17%
G01RMeasuring electric variables6%
G01KMeasuring temperature3%
H10DInorganic electric semiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
8,286,111'Thermal simulation using adaptive 3D and hierarchical grid mechanisms'20128,019,580'Transient thermal analysis'20117,823,102'Thermally aware design modification'20107,353,471'Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance'20087,222,318'Circuit optimization for minimum path timing violations'20077,003,741'Method for determining load capacitance'20066,954,917'Function block architecture for gate array and method for forming an asic'20056,754,877'Method for optimal driver selection'20046,701,506'Method for match delay buffer insertion'20046,701,505'Circuit optimization for minimum path timing violations'20046,701,507'Method for determining a zero-skew buffer insertion point'20046,698,006'Method for balanced-delay clock tree insertion'20046,690,194'Function block architecture for gate array'20046,611,932'Method and apparatus for controlling and observing data in a logic block-based ASIC'20036,242,767'Asic routing architecture'20016,223,313'Method and apparatus for controlling and observing data in a logic block-based asic'20016,014,038'Function block architecture for gate array'20005,406,138'Programmable interconnect architecture using fewer storage cells than switches'19955,400,294'Memory cell with user-selectable logic state on power-up'19955,367,482'High voltage random-access memory cell incorporation level shifter'19945,319,261'Reprogrammable interconnect architecture using fewer storage cells than switches'19945,315,545'High-voltage five-transistor static random access memory cell'19945,301,147'Static random access memory cell with single logic-high voltage level bit-line and address-line drivers'19945,264,741'Low current, fast, CMOS static pullup circuit for static random-access memories'19935,257,239'Memory cell with known state on power-up'19935,239,503'High voltage random-access memory cell incorporating level shifter'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–1995Patents assigned to APTIX CORP (9)· patent assignee history
1993–2012Based in Fremont, CA, US· patent location history
2000–2005Patents assigned to LIGHTSPEED SEMICONDUCTOR CORP (6)· patent assignee history
2004–2007Patents assigned to SEQUENCE DESIGN INC (7)· patent assignee history
2008–2012Patents assigned to GRADIENT DESIGN AUTOMATION INC (4)· patent assignee history
2012Patents assigned to CARNEVALI PAOLO (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APTIX CORP | 9 | 1993–1995 |
| SEQUENCE DESIGN INC | 7 | 2004–2007 |
| LIGHTSPEED SEMICONDUCTOR CORP | 6 | 2000–2005 |
| GRADIENT DESIGN AUTOMATION INC | 4 | 2008–2012 |
| CARNEVALI PAOLO | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 26 | 1993–2012 |