Inventor

Jennifer Wong

Inventor

Fremont, CA, US

Overview

1996–2013

Patent span

Physics

Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing38%

H03KPulse technique36%

G06VImage or video recognition or understanding13%

G11CStatic stores5%

H04LTransmission of digital information, e.g. telegraphic communication3%

G01RMeasuring electric variables2%

H04NPictorial communication, e.g. television2%

H03HImpedance networks, e.g. resonant circuits1%

PatentTitleYear

8,495,122'Programmable device with dynamic DSP architecture'2013 7,882,165'Digital signal processing element having an arithmetic logic unit'2011 7,870,182'Digital signal processing circuit having an adder circuit with carry-outs'2011 7,865,542'Digital signal processing block having a wide multiplexer'2011 7,860,915'Digital signal processing circuit having a pattern circuit for determining termination conditions'2010 7,853,636'Digital signal processing circuit having a pattern detector circuit for convergent rounding'2010 7,853,632'Architectural floorplan for a digital signal processing circuit'2010 7,853,634'Digital signal processing circuit having a SIMD circuit'2010 7,849,119'Digital signal processing circuit having a pattern detector circuit'2010 7,844,653'Digital signal processing circuit having a pre-adder circuit'2010 7,840,630'Arithmetic logic unit circuit'2010 7,840,627'Digital signal processing circuit having input register blocks'2010 7,567,997'Applications of cascading DSP slices'2009 7,480,690'Arithmetic circuit with multiplexed addend inputs'2009 7,472,155'Programmable logic device with cascading DSP slices'2008 7,467,177'Mathematical circuit with dynamic rounding'2008 7,467,175'Programmable logic device with pipelined DSP slices'2008 7,417,918'Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit'2008 7,314,174'Method and system for configuring an integrated circuit'2008 7,286,382'Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability'2007 7,216,277'Self-repairing redundancy for memory blocks in programmable logic devices'2007 7,181,718'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'2007 7,142,442'Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability'2006 7,117,373'Bitstream for configuring a PLD with encrypted design data'2006 7,117,372'Programmable logic device with decryption and structure for preventing design relocation'2006 7,038,519'Digital clock manager having cascade voltage switch logic clock paths'2006 6,981,153'Programmable logic device with method of preventing readback'2005 6,957,340'Encryption key for multi-key encryption in programmable logic device'2005 6,946,874'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'2005 6,931,543'Programmable logic device with decryption algorithm and decryption key'2005 6,803,786'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'2004 6,480,954'Method of time multiplexing a programmable logic device'2002 6,441,641'Programmable logic device with partial battery backup'2002 6,366,117'Nonvolatile/battery-backed key in PLD'2002 6,353,341'Method and apparatus for discriminating against signal interference'2002 6,263,430'Method of time multiplexing a programmable logic device'2001 6,204,695'Clock-gating circuit for reducing power consumption'2001 5,978,260'Method of time multiplexing a programmable logic device'1999 5,959,881'Programmable logic device including configuration data or user data memory slices'1999 5,933,025'Low voltage interface circuit with a high voltage tolerance'1999 5,784,313'Programmable logic device including configuration data or user data memory slices'1998 5,778,439'Programmable logic device with hierarchical confiquration and state storage'1998 5,646,545'Time multiplexed programmable logic device'1997 5,629,637'Method of time multiplexing a programmable logic device'1997 5,600,263'Configuration modes for a time multiplexed programmable logic device'1997 5,583,450'Sequencer for a time multiplexed programmable logic device'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2013Patents assigned to XILINX INC (46)· patent assignee history

1996–2013Based in Fremont, CA, US· patent location history

2013Patents assigned to CHING ALVIN Y (1)· patent assignee history

2013Patents assigned to NEW BERNARD J (1)· patent assignee history

2013Patents assigned to SIMKINS JAMES M (1)· patent assignee history

2013Patents assigned to WONG JENNIFER (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
XILINX INC	46	1996–2013
CHING ALVIN Y	1	2013
NEW BERNARD J	1	2013
SIMKINS JAMES M	1	2013
WONG JENNIFERself	1	2013

Locations

Location	Patents	Span
Fremont, California, US	46	1996–2013