Inventor
Anthony Saporito
Inventor
Highland, NY, US
Overview
Patents· 128 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing90%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
G06VImage or video recognition or understanding1%
G06KGraphical data reading1%
PatentTitleYear
11,113,055Store instruction to store instruction dependency202111,080,052Determining the effectiveness of prefetch instructions202111,010,298Reducing cache transfer overhead in a system202111,010,168Effectiveness and prioritization of prefetches202111,010,066Identifying processor attributes based on detecting a guarded storage event202111,003,452Effectiveness and prioritization of prefetches202110,997,079Method and arrangement for saving cache power202110,963,380Cache miss thread balancing202110,956,337Temporarily suppressing processing of a restrained storage operand request202110,929,142Making precise operand-store-compare predictions to avoid false dependencies202110,929,130Guarded storage event handling during transactional execution202110,884,754Infinite processor thread balancing202110,831,664Cache structure using a logical directory202010,831,674Translation support for a virtual cache202010,831,479Instruction to move data in a right-to-left direction202010,824,426Generating and verifying hardware instruction traces including memory data contents202010,802,986Marking to indicate memory used to back address translation structures202010,740,240Method and arrangement for saving cache power202010,732,858Loading and storing controls regulating the operation of a guarded storage facility202010,725,685Load logical and shift guarded instruction202010,713,048Conditional branch to an indirectly specified location202010,713,168Cache structure using a logical directory202010,698,836Translation support for a virtual cache202010,671,532Reducing cache transfer overhead in a system202010,656,950Spin loop delay instruction202010,621,090Facility for extending exclusive hold of a cache line in private cache202010,599,431Managing backend resources via frontend steering or stalls202010,592,142Toggling modal transient memory access state202010,585,797Operating different processor cache levels202010,585,800Reducing cache transfer overhead in a system202010,579,525Reducing cache transfer overhead in a system202010,579,377Guarded storage event handling during transactional execution202010,572,254Instruction to query cache residency202010,572,384Operating different processor cache levels202010,558,464Infinite processor thread balancing202010,528,472Method and arrangement for saving cache power202010,521,351Temporarily suppressing processing of a restrained storage operand request201910,521,350Determining the effectiveness of prefetch instructions201910,496,292Saving/restoring guarded storage controls in a virtualized environment201910,496,311Run-time instrumentation of guarded storage event processing201910,496,405Generating and verifying hardware instruction traces including memory data contents201910,452,288Identifying processor attributes based on detecting a guarded storage event201910,452,395Instruction to query cache residency201910,445,248Host page management using active guest page table indicators201910,437,597Silent mode and resource reassignment in branch prediction logic201910,430,195Stream based branch prediction index accelerator with power prediction201910,409,609Age management logic201910,379,862Effectiveness and prioritization of prefeteches201910,372,457Effectiveness and prioritization of prefetches201910,365,929Spin loop delay instruction201910,365,928Suppress unnecessary mapping for scratch register201910,353,817Cache miss thread balancing201910,339,049Garbage collection facility grouping infrequently accessed data units in designated transient memory area201910,331,446Generating and verifying hardware instruction traces including memory data contents201910,318,415Garbage collection facility grouping infrequently accessed data units in designated transient memory area201910,318,790Code fingerprint-based processor malfunction detection201910,303,575Time-slice-instrumentation facility201910,303,569Simplified processor sparing201910,282,276Fingerprint-initiated trace extraction201910,275,254Spin loop delay instruction201910,268,582Operating different processor cache levels201910,241,924Reducing over-purging of structures associated with address translation using an array of tags201910,229,061Method and arrangement for saving cache power201910,185,570Dynamic thread sharing in branch prediction structures201910,176,111Host page management using active guest page table indicators201910,168,902Reducing purging of structures associated with address translation201910,169,239Managing a prefetch queue based on priority indications of prefetch requests201910,169,243Reducing over-purging of structures associated with address translation201910,025,592Selectively blocking branch prediction for a predetermined number of instructions201810,019,265Selectively blocking branch prediction for a predetermined number of instructions20189,904,554'Checkpoints for a simultaneous multithreading processor'20189,898,299'Dynamic thread sharing in branch prediction structures'20189,898,294'Selectively blocking branch prediction for a predetermined number of instructions'20189,891,922'Selectively blocking branch prediction for a predetermined number of instructions'20189,836,405Dynamic management of virtual memory blocks exempted from cache memory access20179,792,124'Speculative branch handling for transaction abort'20179,727,484'Dynamic cache memory management with translation lookaside buffer protection'20179,720,694'Silent mode and resource reassignment in branch prediction logic for branch instructions within a millicode routine'20179,715,377'Behavior based code recompilation triggering scheme'20179,697,001'Variable updates of branch prediction states'20179,690,587'Variable updates of branch prediction states'20179,672,045'Checkpoints for a simultaneous multithreading processor'20179,639,370'Software instructed dynamic branch history pattern adjustment'20179,626,293'Single-thread cache miss rate estimation'20179,619,385'Single thread cache miss rate estimation'20179,619,237'Speculative branch handling for transaction abort'20179,606,805'Accuracy of operand store compare prediction using confidence counter'20179,594,566'Accuracy of operand store compare prediction using confidence counter'20179,569,338'Fingerprint-initiated trace extraction'20179,563,430'Dynamic thread sharing in branch prediction structures'20179,547,484'Automated compiler operation verification'20179,524,205'Code fingerprint-based processor malfunction detection'20169,513,909'Variable updates of branch prediction states'20169,495,306'Dynamic management of a processor state with transient cache memory'20169,495,156'Accuracy of operand store compare prediction using confidence counter'20169,495,138'Scheme for verifying the effects of program optimizations'20169,495,157'Fingerprint-based branch prediction'20169,454,377'Speculative branch handling for transaction abort'20169,442,738'Restricting processing within a processor to facilitate transaction completion'20169,442,737'Restricting processing within a processor to facilitate transaction completion'20169,424,044'Silent mode and resource reassignment in branch prediction logic for branch instructions within a millicode routine'20169,411,664'Fingerprint-based processor parameter management'20169,396,125'Dynamic management of memory ranges exempted from cache memory access'20169,395,961'Fingerprint-based code version selection'20169,250,909'Fast index tree for accelerated branch prediction'20169,250,912'Fast index tree for accelerated branch prediction'20169,152,425'Mitigating instruction prediction latency with independently filtered presence predictors'20159,152,424'Mitigating instruction prediction latency with independently filtered presence predictors'20159,135,012'Instruction filtering'20159,135,013'Instruction filtering'20159,021,240'System and method for Controlling restarting of instruction fetching using speculative address computations'20158,972,665'Cache set selective power up'20158,874,885'Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs'20148,443,176'Method, system, and computer program product for reducing cache memory pollution'20137,913,068'System and method for providing asynchronous dynamic millicode entry prediction'20117,882,338'Method, system and computer program product for an implicit predicted return from a predicted subroutine'20117,831,775'System and method for tracking changes in L1 data cache directory'20107,822,954'Methods, systems, and computer program products for recovering from branch prediction latency'20107,814,374'System and method for the capture and preservation of intermediate error state data'20107,805,634'Error accumulation register, error accumulation method, and error accumulation system'20107,752,354'Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor'20107,603,543'Method, apparatus and program product for enhancing performance of an in-order processor with long stalls'20097,571,283'Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch'20097,401,186'System and method for tracking changes in L1 data cache directory'20087,380,062'Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch'20087,318,127'Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor'20087,284,094'Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class'20077,111,196'System and method for providing processor recovery in a multi-core system'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2021Patents assigned to IBM (128)· patent assignee history
2006Based in Wappingers Falls, NY, US· patent location history
2007–2010Based in Hyde Park, NY, US· patent location history
2010–2021Based in Highland, NY, US· patent location history
2013–2018Patents assigned to SAPORITO ANTHONY (9)· patent assignee history
2013–2016Patents assigned to PRASKY BRIAN R (7)· patent assignee history
2013–2018Patents assigned to BONANNO JAMES J (6)· patent assignee history
2015–2016Patents assigned to ALEXANDER KHARY J (2)· patent assignee history
2019–2020Based in Poughkeepsie, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 128 | 2006–2021 |
| SAPORITO ANTHONYself | 9 | 2013–2018 |
| PRASKY BRIAN R | 7 | 2013–2016 |
| BONANNO JAMES J | 6 | 2013–2018 |
| ALEXANDER KHARY J | 2 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Highland, New York, US | 116 | 2010–2021 |
| Hyde Park, New York, US | 8 | 2007–2010 |
| Poughkeepsie, New York, US | 3 | 2019–2020 |
| Wappingers Falls, New York, US | 1 | 2006 |