Inventor
William T. Motsiff
Inventor
Essex Junction, VT, US
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1059%
H10DInorganic electric semiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H05KPrinted circuits3%
G01RMeasuring electric variables2%
G11CStatic stores2%
H01HElectric switches2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
B23KSoldering or unsoldering1%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds1%
PatentTitleYear
8,044,510'Product and method for integration of deep trench mesh and structures under a bond pad'20117,981,732'Programming of laser fuse'20117,786,549'Antifuse structure and system for closing thereof'20107,704,876'Dual damascene interconnect structures having different materials for line and via conductors'20107,521,336'Crack stop for low K dielectrics'20097,482,258'Product and method for integration of deep trench mesh and structures under a bond pad'20097,384,824'Structure and programming of laser fuse'20087,358,148'Adjustable self-aligned air gap dielectric for low capacitance wiring'20087,335,577'Crack stop for low K dielectrics'20087,300,867'Dual damascene interconnect structures having different materials for line and via conductors'20077,207,096'Method of manufacturing high performance copper inductors with bond pads'20077,115,968'Method of closing an antifuse using laser energy'20067,071,532'Adjustable self-aligned air gap dielectric for low capacitance wiring'20067,064,409'Structure and programming of laser fuse'20067,045,472'Method and apparatus for selectively altering dielectric properties of localized semiconductor device regions'20066,991,971'Method for fabricating a triple damascene fuse'20066,982,227'Single and multilevel rework'20066,958,540'Dual damascene interconnect structures having different materials for line and via conductors'20056,946,379'Insulative cap for laser fusing'20056,924,210'Chip dicing'20056,909,296'Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting'20056,876,058'Wiring protection element for laser deleted tungsten fuse'20056,872,648'Reduced splattering of unpassivated laser fuses'20056,844,747'Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting'20056,844,609'Antifuse with electrostatic assist'20056,835,973'Antifuse for use with low dielectric foam insulators'20046,827,868'Thinning of fuse passivation after C4 formation'20046,815,838'Laser alignment target and method'20046,806,578'Copper pad structure'20046,798,066'Heat dissipation from IC interconnects'20046,784,516'Insulative cap for laser fusing'20046,773,952'Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces'20046,746,947'Post-fuse blow corrosion prevention structure for copper fuses'20046,743,710'Stacked fill structures for support of dielectric layers'20046,734,047'Thinning of fuse passivation after C4 formation'20046,713,838'Inductive fuse for semiconductor device'20046,674,168'Single and multilevel rework'20046,667,533'Triple damascene fuse'20036,661,106'Alignment mark structure for laser fusing and method of use'20036,605,526'Wirebond passivation pad connection using heated capillary'20036,573,538'Semiconductor device with internal heat dissipation'20036,559,543'Stacked fill structures for support of dielectric layers'20036,512,292'Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces'20036,498,056'Apparatus and method for antifuse with electrostatic assist'20026,498,385'Post-fuse blow corrosion prevention structure for copper fuses'20026,496,053'Corrosion insensitive fusible link using capacitance sensing for semiconductor devices'20026,492,207'Method for making a pedestal fuse'20026,472,230'Re-settable tristate programmable device'20026,458,630'Antifuse for use with low k dielectric foam insulators'20026,455,914'Pedestal fuse'20026,440,834'Method and structure for a semiconductor fuse'20026,426,557'Self-aligned last-metal C4 interconnection layer for Cu technologies'20026,420,772'Re-settable tristate programmable device'20026,375,159'High laser absorption copper fuse and method for making the same'20026,340,630'Method for making interconnect for low temperature chip attachment'20026,335,229'Inductive fuse for semiconductor device'20026,261,873'Pedestal fuse'20016,249,038'Method and structure for a semiconductor fuse'20016,127,735'Interconnect for low temperature chip attachment'20006,093,630'Semi-conductor personalization structure and method'20005,897,336'Direct chip attach for low alpha emission interconnect system'19995,883,435'Personalization structure for semiconductor devices'19995,795,819'Integrated pad and fuse structure for planar copper metallurgy'19985,731,624'Integrated pad and fuse structure for planar copper metallurgy'19985,719,070'Metallization composite having nickel intermediate/interface'19985,457,345'Metallization composite having nickle intermediate/interface'19954,590,258'Polyamic acid copolymer system for improved semiconductor manufacturing'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2011Patents assigned to IBM (67)· patent assignee history
1986–2011Based in Essex Junction, VT, US· patent location history
2005Patents assigned to INFINEON TECHNOLOGIES AG (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 67 | 1986–2011 |
| INFINEON TECHNOLOGIES AG | 1 | 2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 67 | 1986–2011 |