Inventor
Hsingya Arthur Wang
Inventor
San Jose, CA, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices29%
H10DInorganic electric semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G11CStatic stores9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
Y10TTechnical subjects covered by former us classification3%
H01LSemiconductor devices2%
PatentTitleYear
8,946,003'Method of forming transistors with ultra-short gate feature'20158,288,219'Method of forming a non-volatile memory cell using off-set spacers'20127,250,341'Flash memory device having poly spacers'20077,202,134'Method of forming transistors with ultra-short gate feature'20077,160,774'Method of forming polysilicon layers in non-volatile memory'20077,154,141'Source side programming'20066,911,370'Flash memory device having poly spacers'20056,876,582'Flash memory cell erase scheme using both source and channel regions'20056,849,489'Method for forming transistors with ultra-short gate feature'20056,818,504'Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications'20046,812,515'Polysilicon layers structure and method of forming same'20046,777,741'Non-volatile memory cells with selectively formed floating gate'20046,746,906'Transistor with ultra-short gate feature and method of fabricating the same'20046,559,008'Non-volatile memory cells with selectively formed floating gate'20036,509,237'Flash memory cell fabrication sequence'20036,169,693'Self-convergence of post-erase threshold voltages in a flash memory cell using transient response'20016,043,123'Triple well flash memory fabrication process'20006,026,026'Self-convergence of post-erase threshold voltages in a flash memory cell using transient response'20005,989,938'Method of fabricating topside structure of a semiconductor device'19995,981,364'Method of forming a silicon gate to produce silicon devices with improved performance'19995,920,506'Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents'19995,908,318'Method of forming low capacitance interconnect structures on semiconductor substrates'19995,899,726'Method of forming oxide isolation in a semiconductor device'19995,882,985'Reduction of field oxide step height during semiconductor fabrication'19995,866,467'Method of improving oxide isolation in a semiconductor device'19995,831,901'Method of programming a memory cell to contain multiple values'19985,818,082'E.sup.2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof'19985,776,811'Simplified process for fabricating flash eeprom cells'19985,763,307'Block select transistor and method of fabrication'19985,747,882'Device including means for preventing tungsten silicide lifting, and method of fabrication thereof'19985,728,453'Method of fabricating topside structure of a semiconductor device'19985,656,513'Nonvolatile memory cell formed using self aligned source implant'19975,553,018'Nonvolatile memory cell formed using self aligned source implant'19965,013,675'Method of forming and removing polysilicon lightly doped drain spacers'19914,992,391'Process for fabricating a control gate for a floating gate FET'19914,635,347'Method of fabricating titanium silicide gate electrodes and interconnections'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987–1999Patents assigned to ADVANCED MICRO DEVICES INC (17)· patent assignee history
1987–2015Based in San Jose, CA, US· patent location history
1996–2001Based in Saratoga, CA, US· patent location history
1999–2006Patents assigned to HYUNDAI ELECTRONICS AMERICA (5)· patent assignee history
2003–2004Patents assigned to HYNIX SEMICONDUCTOR AMERICA INC (4)· patent assignee history
2004–2012Patents assigned to HYNIX SEMICONDUCTOR INC (9)· patent assignee history
2012–2015Patents assigned to CHOU KAI-CHENG (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 17 | 1987–1999 |
| HYNIX SEMICONDUCTOR INC | 9 | 2004–2012 |
| HYUNDAI ELECTRONICS AMERICA | 5 | 1999–2006 |
| HYNIX SEMICONDUCTOR AMERICA INC | 4 | 2003–2004 |
| CHOU KAI-CHENG | 2 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 18 | 1987–2015 |
| Saratoga, California, US | 18 | 1996–2001 |