Inventor
David M. Dobuzinsky
Inventor
Hopewell Junction, NY, US
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10DInorganic electric semiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10BElectronic memory devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
C23CCoating metallic material5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
8,772,850'Embedded DRAM memory cell with additional patterning layer for improved strap formation'20148,426,268'Embedded DRAM memory cell with additional patterning layer for improved strap formation'20138,008,713'Vertical SOI trench SONOS cell'20118,003,488'Shallow trench isolation structure compatible with SOI embedded DRAM'20117,893,485'Vertical SOI trench SONOS cell'20117,871,893'Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices'20117,592,245'Poly filled substrate contact on SOI structure'20097,560,360'Methods for enhancing trench capacitance and trench capacitor'20097,514,323'Vertical SOI trench SONOS cell'20097,394,131'STI formation in semiconductor device including SOI and bulk silicon regions'20087,358,172'Poly filled substrate contact on SOI structure'20087,118,986'STI formation in semiconductor device including SOI and bulk silicon regions'20067,087,532'Formation of controlled sublithographic structures'20066,964,897'SOI trench capacitor cell incorporating a low-leakage floating body array transistor'20056,960,523'Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device'20056,890,815'Reduced cap layer erosion for borderless contacts'20056,887,785'Etching openings of different depths using a single mask layer method and structure'20056,869,542'Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials'20056,809,027'Self-aligned borderless contacts'20046,806,200'Method of improving etch uniformity in deep silicon etching'20046,806,177'Method of making self-aligned borderless contacts'20046,740,568'Method to enhance epitaxial regrowth in amorphous silicon contacts'20046,740,539'Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates'20046,656,375'Selective nitride: oxide anisotropic etch process'20036,570,256'Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates'20036,518,151'Dual layer hard mask for eDRAM gate etch process'20036,208,008'Integrated circuits having reduced stress in metallization'20016,207,353'Resist formulation which minimizes blistering during etching'20016,153,474'Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate'20006,093,281'Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers'20006,066,570'Method and apparatus for preventing formation of black silicon on edges of wafers'20006,046,487'Shallow trench isolation with oxide-nitride/oxynitride liner'20006,014,310'High dielectric TiO.sub.2 -SiN composite films for memory applications'20005,998,100'Fabrication process using a multi-layer antireflective layer'19995,939,335'Method for reducing stress in the metallization of an integrated circuit'19995,899,724'Method for fabricating a titanium resistor'19995,885,899'Method of chemically mechanically polishing an electronic component using a non-selective ammonium hydroxide slurry'19995,876,788'High dielectric TiO.sub.2 -SiN composite films for memory applications'19995,763,315'Shallow trench isolation with oxide-nitride/oxynitride liner'19985,759,746'Fabrication process using a thin resist'19985,747,866'Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures'19985,656,535'Storage node process for deep trench-based DRAM'19975,643,823'Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures'19975,622,596'High density selective SiO.sub.2 :Si.sub.3 N.sub.4 etching using a stoichiometrically altered nitride etch stop'19975,563,105'PECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming element'19965,539,154'Fluorinated silicon nitride films'19965,536,360'Method for etching boron nitride'19965,468,687'Method of making TA.sub.2 O.sub.5 thin film by low temperature ozone plasma annealing (oxidation)'19955,462,812'Fluorinated silicon nitride films'19955,455,204'Thin capacitor dielectric by rapid thermal processing'19955,412,246'Low temperature plasma oxidation process'19955,330,935'Low temperature plasma oxidation process'19945,217,567'Selective etching process for boron nitride films'19935,204,138'Plasma enhanced CVD process for fluorinated silicon nitride films'19935,173,452'Process for the vapor deposition of polysilanes photoresists'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2013Patents assigned to DOBUZINSKY DAVID M (2)· patent assignee history
1992–1995Based in Essex Junction, VT, US· patent location history
1993–2014Patents assigned to IBM (52)· patent assignee history
1995–2011Based in Hopewell Junction, NY, US· patent location history
1997–2000Patents assigned to SIEMENS AG (6)· patent assignee history
1998–1999Patents assigned to TOSHIBA KK (3)· patent assignee history
2003–2004Patents assigned to INFINEON TECHNOLOGIES AG (3)· patent assignee history
2003–2014Based in New Windsor, NY, US· patent location history
2013Based in East Meadow, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 52 | 1993–2014 |
| SIEMENS AG | 6 | 1997–2000 |
| INFINEON TECHNOLOGIES AG | 3 | 2003–2004 |
| TOSHIBA KK | 3 | 1998–1999 |
| DOBUZINSKY DAVID Mself | 2 | 1992–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 28 | 1995–2011 |
| New Windsor, New York, US | 21 | 2003–2014 |
| Essex Junction, VT, US | 5 | 1992–1995 |
| East Meadow, New York, US | 1 | 2013 |