Inventor
Michael G. Lee
Inventor
San Jose, CA, US
Overview
Patents· 81 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H05KPrinted circuits21%
G02BOptical elements, systems or apparatus9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
Y10TTechnical subjects covered by former us classification8%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein6%
H04LTransmission of digital information, e.g. telegraphic communication3%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
H01GCapacitors2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,521,717Representation of weight values in an artificial neural network using inter-group indexing20199,496,248'Interposer for integrated circuit chip package'20168,975,092'Method and system for controlling chip warpage during bonding'20158,859,335'Method and system for controlling chip inclination during flip-chip mounting'20148,633,592'Hybrid interconnect technology'20148,487,428'Method and system for providing a reliable semiconductor assembly'20138,236,606'Method and system for providing a low-profile semiconductor assembly'20127,860,079'Method and apparatus to protect wireless networks from unsolicited packets triggering radio resource consumption'20107,855,377'Alignment structures for an optical assembly'20107,781,867'Method and system for providing an aligned semiconductor assembly'20107,742,666'Optical beam splitter'20107,609,968'Secure analog communication system using time and wavelength scrambling'20097,522,783'Optical interconnect apparatuses and electro-optic modulators for processing systems'20097,516,485'Method and apparatus for securely transmitting encrypted data through a firewall and for monitoring user traffic'20097,504,014'High density interconnections with nanowiring'20097,453,058'Optical bumps for low-loss interconnection between a device and its supported substrate and related methods'20087,403,672'Integrated linear polarizer'20087,395,423'Security association storage and recovery in group key management'20087,376,295'Opto-electronic processors with reconfigurable chip-to-chip optical interconnections'20087,350,233'Fast re-establishment of communications for virtual private network devices'20087,343,054'Integrated electro-optic module for high speed data transmission'20087,283,220'Methods and apparatuses for measuring the refractive index and other optical properties of liquids, gels, and solids'20077,275,109'Network communication authentication'20077,257,217'Call features for automatic call distribution system'20077,229,219'Apparatuses and methods for integrating opto-electric components into the optical pathways of routing substrates with precision optical coupling and compact electrical interconnection'20077,209,621'Optical apparatuses providing optical interconnections among a plurality of electronic components'20077,171,065'Compact optical devices and methods for making the same'20077,083,869'Methods of forming LaNiO3 conductive layers, ferro-electric devices with LaNiO3 layers, and precursor formation solutions'20067,035,489'Thin film electro-optical deflector device and a method of fabrication of such a device'20066,922,508'Optical switching apparatus with adiabatic coupling to optical fiber'20056,898,343'Optical switching apparatus and method for fabricating'20056,885,781'Thin film electro-optical deflector device and a method of fabrication of such a device'20056,884,313'Method and system for joining and an ultra-high density interconnect'20056,866,741'Method for joining large substrates'20056,845,184'Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making'20056,823,097'Optical switching apparatus with divergence correction'20046,800,169'Method for joining conductive structures and an electrical conductive article'20046,733,685'Methods of planarizing structures on wafers and substrates by polishing'20046,730,358'Method for depositing conductive paste using stencil'20046,690,845'Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making'20046,662,443'Method of fabricating a substrate with a via connection'20036,611,635'Opto-electronic substrates with electrical and optical interconnections and methods for making'20036,592,943'Stencil and method for depositing solder'20036,543,674'Multilayer interconnection and method'20036,518,096'Interconnect assembly and Z-connection method for fine pitch substrates'20036,469,394'Conductive interconnect structures and methods for forming conductive interconnect structures'20026,444,921'Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like'20026,428,942'Multilayer circuit structure build up method'20026,343,171'Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making'20026,239,485'Reduced cross-talk noise high density signal interposer with power and ground wrap'20016,226,171'Power conducting substrates with high-yield integrated substrate capacitor'20016,197,664'Method for electroplating vias or through holes in substrates having conductors on both sides'20016,187,652'Method of fabrication of multiple-layer high density substrate'20016,163,957'Multilayer laminated substrates with high density interconnects and methods of making the same'20006,146,241'Apparatus for uniform chemical mechanical polishing by intermittent lifting and reversible rotation'20006,102,710'Controlled impedance interposer substrate and method of making'20006,081,026'High density signal interposer with power and ground wrap'20006,050,832'Chip and board stress relief interposer'20006,047,637'Method of paste printing using stencil and masking layer'20006,025,244'Self-aligned patterns by chemical-mechanical polishing particularly suited to the formation of MCM capacitors'20006,019,665'Controlled retention of slurry in chemical mechanical polishing'20005,930,890'Structure and fabrication procedure for a stable post'19995,916,453'Methods of planarizing structures on wafers and substrates by polishing'19995,891,354'Methods of etching through wafers and substrates with a composite etch stop layer'19995,872,696'Sputtered and anodized capacitors capable of withstanding exposure to high temperatures'19995,854,534'Controlled impedence interposer substrate'19985,778,529'Method of making a multichip module substrate'19985,746,903'Wet chemical processing techniques for plating high aspect ratio features'19985,722,162'Fabrication procedure for a stable post'19985,544,017'Multichip module substrate'19965,476,430'Exercise treadmill with variable response to foot impact induced speed variation'19955,454,161'Through hole interconnect substrate fabrication process'19955,419,038'Method for fabricating thin-film interconnector'19955,406,446'Thin film capacitor'19955,323,520'Process for fabricating a substrate with thin film capacitor'1994D0300359'Recorder for a medical monitor'1989D0299861'Medical monitor'1989D0296240'Medical monitor'19884,677,431'Raster display smoothing technique'19874,379,312'Control system for audio-visual projector'19834,363,055'Control system for audio-visual projector'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982–1983Patents assigned to INDAL CORP (2)· patent assignee history
1982–1989Based in Redmond, WA, US· patent location history
1987–1989Patents assigned to SPACELABS INC (4)· patent assignee history
1994–2019Patents assigned to FUJITSU LTD (66)· patent assignee history
1994–2013Based in San Jose, CA, US· patent location history
1995Based in Sultan, WA, US· patent location history
2007–2010Patents assigned to NORTEL NETWORKS LTD (7)· patent assignee history
2007–2010Based in Ottawa, CA· patent location history
2012–2014Patents assigned to LEE MICHAEL G (3)· patent assignee history
2014–2019Based in Saratoga, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 66 | 1994–2019 |
| NORTEL NETWORKS LTD | 7 | 2007–2010 |
| SPACELABS INC | 4 | 1987–1989 |
| LEE MICHAEL Gself | 3 | 2012–2014 |
| INDAL CORP | 2 | 1982–1983 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 62 | 1994–2013 |
| Ottawa, CA | 7 | 2007–2010 |
| Redmond, Washington, US | 6 | 1982–1989 |
| Saratoga, California, US | 5 | 2014–2019 |
| Sultan, Washington, US | 1 | 1995 |