Inventor
James Yamaguchi
Inventor
Laguna Niguel, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H05KPrinted circuits18%
Y10TTechnical subjects covered by former us classification15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H01LSemiconductor devices5%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
9,741,680'Wire bond through-via structure and method'20179,431,275'Wire bond through-via structure and method'20168,637,985'Anti-tamper wrapper interconnect method and a device'20148,637,140'Method for defining an electrically conductive metal structure on a three-dimensional element and a device made from the method'20148,609,473'Method for fabricating a neo-layer using stud bumped bare die'2013RE043877'Method for precision integrated circuit die singulation using differential etch rates'20127,786,562'Stackable semiconductor chip layer comprising prefabricated trench interconnect vias'20107,335,576'Method for precision integrated circuit die singulation using differential etch rates'20087,239,012'Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers'20077,127,807'Process of manufacturing multilayer modules'20066,797,537'Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers'20046,784,547'Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers'20046,734,370'Multilayer modules with flexible substrates'20046,717,061'Stacking of multilayer modules'20046,560,109'Stack of multilayer modules with heat-focusing metal layer'20036,117,704'Stackable layers containing encapsulated chips'20006,072,234'Stack of equal layer neo-chips containing encapsulated IC chips of different sizes'20005,953,588'Stackable layers containing encapsulated IC chips'19995,123,164'Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture'19925,030,499'Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–1992Based in Lake Forest, CA, US· patent location history
1999–2008Patents assigned to IRVINE SENSORS CORP (11)· patent assignee history
1999–2016Based in Laguna Niguel, CA, US· patent location history
2010–2016Patents assigned to BOYD W ERIC (6)· patent assignee history
2010–2016Patents assigned to YAMAGUCHI JAMES (6)· patent assignee history
2013–2016Patents assigned to BINDRUP RANDY (3)· patent assignee history
2013–2014Patents assigned to ISC8 INC (2)· patent assignee history
2014Based in Laguna Nigel, CA, US· patent location history
2017Based in Costa Mesa, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IRVINE SENSORS CORP | 11 | 1999–2008 |
| BOYD W ERIC | 6 | 2010–2016 |
| YAMAGUCHI JAMESself | 6 | 2010–2016 |
| BINDRUP RANDY | 3 | 2013–2016 |
| ISC8 INC | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Laguna Niguel, California, US | 16 | 1999–2016 |
| Lake Forest, California, US | 2 | 1991–1992 |
| Costa Mesa, California, US | 1 | 2017 |
| Laguna Nigel, California, US | 1 | 2014 |