Inventor

Hao Fang

Inventor

Cupertino, CA, US

Overview

1995–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 79 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices30%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H10DInorganic electric semiconductor devices16%

G11CStatic stores9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

G11BInformation storage based on relative movement between record carrier and transducer5%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G06FElectric digital data processing4%

G01RMeasuring electric variables2%

H03FAmplifiers2%

PatentTitleYear

10,734,016Pulse-based writing for magnetic storage media2020 10,713,330Optimized browser render process2020 9,984,130Batch-optimized render and fetch architecture utilizing a virtual clock2018 9,785,720'Script optimized browser rendering process'2017 9,520,400'NOR structure flash memory and manufacturing method thereof'2016 8,507,969'Method and system for providing contact to a first polysilicon layer in a flash memory device'2013 8,329,530'Method and system for providing contact to a first polysilicon layer in a flash memory device'2012 8,183,619'Method and system for providing contact to a first polysilicon layer in a flash memory device'2012 7,692,887'Method and apparatus for measuring resistance of a resistive sensor'2010 7,672,165'Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'2010 7,466,508'Impedance-matched write circuit with shunted matching resistor'2008 7,436,703'Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'2008 7,362,615'Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices'2008 7,221,008'Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory'2007 7,167,330'Over-writing data in a recording system'2007 7,141,469'Method of forming poly insulator poly capacitors by using a self-aligned salicide process'2006 7,116,174'Base current compensation circuit for a bipolar junction transistor'2006 7,106,536'Write head demagnetizer'2006 7,019,923'Pre-amplifier employing transistors having a diminished breakdown voltage and a disk drive and a Thevenin writer employing the same'2006 6,979,619'Flash memory device and a method of fabrication thereof'2005 6,815,292'Flash memory having improved core field isolation in select gate regions'2004 6,667,511'NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration'2003 6,638,358'Method and system for processing a semiconductor device'2003 6,610,580'Flash memory array and a method and system of fabrication thereof'2003 6,603,211'Method and system for providing a robust alignment mark at thin oxide layers'2003 6,602,776'Method and system for providing a polysilicon stringer monitor'2003 6,514,830'Method of manufacturing high voltage transistor with modified field implant mask'2003 6,495,435'Method for improved control of lines adjacent to a select gate using a mask assist feature'2002 6,492,229'Semiconductor device having reduced field oxide recess and method of fabrication'2002 6,472,327'Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication'2002 6,448,593'Type-1 polysilicon electrostatic discharge transistors'2002 6,448,594'Method and system for processing a semiconductor device'2002 6,448,609'Method and system for providing a polysilicon stringer monitor'2002 6,445,051'Method and system for providing contacts with greater tolerance for misalignment in a flash memory'2002 6,436,778'Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process'2002 6,429,479'Nand flash memory with specified gate oxide thickness'2002 6,420,240'Method for reducing the step height of shallow trench isolation structures'2002 6,417,990'Composite core structure for high efficiency writer'2002 6,410,949'Flash memory device with monitor structure for monitoring second gate over-etch'2002 6,376,309'Method for reduced gate aspect ratio to improve gap-fill after spacer etch'2002 6,372,577'Core cell structure and corresponding process for NAND type performance flash memory device'2002 6,369,433'High voltage transistor with low body effect and low leakage'2002 6,362,049'High yield performance semiconductor process flow for NAND flash memory products'2002 6,351,017'High voltage transistor with modified field implant mask'2002 6,350,627'Interlevel dielectric thickness monitor for complex semiconductor chips'2002 6,346,737'Shallow trench isolation process particularly suited for high voltage circuits'2002 6,323,047'Method for monitoring second gate over-etch in a semiconductor device'2001 6,316,293'Method of forming a nand-type flash memory device having a non-stacked gate transistor structure'2001 6,312,991'Elimination of poly cap easy poly 1 contact for NAND product'2001 6,306,706'Method and system for fabricating a flash memory array'2001 6,300,658'Method for reduced gate aspect ration to improve gap-fill after spacer etch'2001 6,235,586'Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications'2001 6,228,782'Core field isolation for a NAND flash memory'2001 6,218,689'Method for providing a dopant level for polysilicon for flash memory devices'2001 6,211,058'Semiconductor device with multiple contact sizes'2001 6,188,606'Multi state sensing of NAND memory cells by varying source bias'2001 6,188,113'High voltage transistor with high gated diode breakdown, low body effect and low leakage'2001 6,177,322'High voltage transistor with high gated diode breakdown voltage'2001 6,177,345'Method of silicide film formation onto a semiconductor substrate'2001 6,175,522'Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory device'2001 6,166,951'Multi state sensing of NAND memory cells by applying reverse-bias voltage'2000 6,159,795'Low voltage junction and high voltage junction optimization for flash memory'2000 6,143,612'High voltage transistor with high gated diode breakdown, low body effect and low leakage'2000 6,143,608'Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation'2000 6,133,746'Method for determining a reliable oxide thickness'2000 6,072,191'Interlevel dielectric thickness monitor for complex semiconductor chips'2000 6,057,193'Elimination of poly cap for easy poly1 contact for NAND product'2000 6,023,085'Core cell structure and corresponding process for NAND-type high performance flash memory device'2000 5,994,239'Manufacturing process to eliminate polystringers in high density nand-type flash memory devices'1999 5,994,780'Semiconductor device with multiple contact sizes'1999 5,991,202'Method for reducing program disturb during self-boosting in a NAND flash memory'1999 5,978,272'Nonvolatile memory structure for programmable logic devices'1999 5,858,844'Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process'1999 5,708,588'Flash EEPROM memory with improved discharged speed using substrate bias and method therefor'1998 5,617,357'Flash EEPROM memory with improved discharge speed using substrate bias and method therefor'1997 5,606,518'Test method for predicting hot-carrier induced leakage over time in short-channel IGFETS and products designed in accordance with test results'1997 5,600,578'Test method for predicting hot-carrier induced leakage over time in short-channel IGFETs and products designed in accordance with test results'1997 5,491,657'Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells'1996 5,457,336'Non-volatile memory structure including protection and structure for maintaining threshold stability'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2005Patents assigned to ADVANCED MICRO DEVICES INC (57)· patent assignee history

1995–2013Based in Cupertino, CA, US· patent location history

2000–2002Patents assigned to FUJITSU LTD (10)· patent assignee history

2002–2008Based in Savage, MN, US· patent location history

2006–2010Patents assigned to AGERE SYSTEMS INC (6)· patent assignee history

2006–2010Based in Shanghai, CN· patent location history

2007–2010Patents assigned to SANDISK CORP (4)· patent assignee history

2012–2013Patents assigned to CHANG MARK S (3)· patent assignee history

2017–2020Based in Beijing, CN· patent location history

2020Based in Eden Praire, MN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	57	1995–2005
FUJITSU LTD	10	2000–2002
AGERE SYSTEMS INC	6	2006–2010
SANDISK CORP	4	2007–2010
CHANG MARK S	3	2012–2013

Locations

Location	Patents	Span
Cupertino, California, US	63	1995–2013
Savage, Minnesota, US	6	2002–2008
Shanghai, CN	4	2006–2010
Beijing, CN	3	2017–2020
Eden Praire, Minnesota, US	1	2020