Inventor
Uwe Paul Schroeder
Inventor
Dresden, DE
Overview
Patents· 58 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices18%
H10BElectronic memory devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G06FElectric digital data processing6%
H01LSemiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H01GCapacitors2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,311,186Three-dimensional pattern risk scoring201910,276,674Method of forming a gate contact structure and source/drain contact structure for a semiconductor device201910,248,754Multi-stage pattern recognition in circuit designs201910,095,826Feed-forward for silicon inspections (DFM2CFM : design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM : silicon to design) guided by marker classification, sampling, and higher dimensional analysis201810,055,535Method, system and program product for identifying anomalies in integrated circuit design layouts20189,547,741'Methods, apparatus, and system for using filler cells in design of integrated circuit devices'20179,437,420'Capacitors including amorphous dielectric layers and methods of forming the same'20169,245,087'Methods, apparatus and system for reduction of power consumption in a semiconductor device'20169,195,142'Lithography masks, systems, and manufacturing methods'20158,853,791'SRAM memory cell having a dogleg shaped gate electrode structure'20148,663,877'Lithography masks, systems, and manufacturing methods'20148,344,438'Electrode of an integrated circuit'20138,247,845'Electrostatic discharge (ESD) protection circuit placement in semiconductor devices'20128,153,335'Lithography masks, systems, and manufacturing methods'20128,003,305'Method for patterning a semiconductor wafer'20117,985,676'Method of making a contact in a semiconductor device'20117,939,137'Method and device for producing parts having a sealing layer on the surface, and corresponding parts'20117,859,645'Masks and methods of manufacture thereof'20107,846,616'Lithography masks and methods'20107,838,959'Radio frequency (RF) circuit placement in semiconductor devices'20107,723,771'Zirconium oxide based capacitor and process to manufacture the same'20107,678,704'Method of making a contact in a semiconductor device'20107,666,752'Deposition method for a transition-metal-containing dielectric'20107,648,805'Masks and methods of manufacture thereof'20107,531,406'Method for fabricating an electrical component'20097,405,024'Lithographic mask, and method for covering a mask layer'20087,268,080'Method for printing contacts on a substrate'20077,259,107'Method of forming isolated features of semiconductor devices'20077,224,030'Method and apparatus for producing rectangular contact holes utilizing side lobe formation'20077,157,371'Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices'20077,157,194'Method for exposing a substrate with a structure pattern which compensates for the optical proximity effect'20077,074,528'Effective assist pattern for nested and isolated contacts'20067,049,241'Method for forming a trench in a layer or a layer stack on a semiconductor wafer'20066,897,943'Method and apparatus for aerial image improvement in projection lithography using a phase shifting aperture'20056,767,682'Method for producing quadratic contact holes utilizing side lobe formation'20046,740,555'Semiconductor structures and manufacturing methods'20046,740,595'Etch process for recessing polysilicon in trench structures'20046,620,724'Low resistivity deep trench fill for DRAM and EDRAM applications'20036,613,642'Method for surface roughness enhancement in semiconductor capacitor manufacturing'20036,605,860'Semiconductor structures and manufacturing methods'20036,605,838'Process flow for thick isolation collar with reduced length'20036,605,396'Resolution enhancement for alternating phase shift masks'20036,599,798'Method of preparing buried LOCOS collar in trench DRAMS'20036,590,657'Semiconductor structures and manufacturing methods'20036,576,550'Via first dual damascene process for copper metallization'20036,559,002'Rough oxide hard mask for DT surface area enhancement for DT DRAM'20036,548,357'Modified gate processing for optimized definition of array and logic devices on same chip'20036,540,938'Liquid crystalline light-modulating device'20036,498,061'Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation'20026,486,024'Integrated circuit trench device with a dielectric collar stack, and method of forming thereof'20026,451,662'Method of forming low-leakage on-chip capacitor'20026,426,253'Method of forming a vertically oriented device in an integrated circuit'20026,403,423'Modified gate processing for optimized definition of array and logic devices on same chip'20026,399,490'Highly conformal titanium nitride deposition process for high aspect ratio structures'20026,379,869'Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning'20026,355,503'Method for producing square contact holes utilizing side lobe formation'20026,335,247'Integrated circuit vertical trench device and method of forming thereof'20026,316,168'Top layer imaging lithography for semiconductor processing'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2004Based in Poughkeepsie, NY, US· patent location history
2002–2015Patents assigned to INFINEON TECHNOLOGIES AG (36)· patent assignee history
2002–2011Patents assigned to IBM (14)· patent assignee history
2002–2016Based in Dresden, DE· patent location history
2002–2007Based in Fishkill, NY, US· patent location history
2003Patents assigned to INFINEON TECHNOLOGIES CORP (4)· patent assignee history
2007–2015Based in Lake Carmel, NY, US· patent location history
2012–2014Patents assigned to SCHROEDER UWE PAUL (4)· patent assignee history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (7)· patent assignee history
2018–2019Based in Santa Cruz, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 36 | 2002–2015 |
| IBM | 14 | 2002–2011 |
| GLOBALFOUNDRIES INC | 7 | 2016–2019 |
| INFINEON TECHNOLOGIES CORP | 4 | 2003 |
| SCHROEDER UWE PAULself | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dresden, DE | 15 | 2002–2016 |
| Lake Carmel, New York, US | 13 | 2007–2015 |
| Fishkill, New York, US | 10 | 2002–2007 |
| Santa Cruz, California, US | 5 | 2018–2019 |
| Poughkeepsie, New York, US | 3 | 2001–2004 |