Inventor
Mark A. Holler
Inventor
Palo Alto, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Nprimary
G06NComputing arrangements based on specific computational models20%
H10DInorganic electric semiconductor devices19%
G11CStatic stores12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H10BElectronic memory devices8%
G06FElectric digital data processing7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
A63FCard, board, or roulette games2%
PatentTitleYear
7,152,172'Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time'20066,665,805'Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time'20036,554,433'Office workspace having a multi-surface projection and a multi-camera system'20036,538,649'Computer vision control variable transformation'20036,145,375'Timing device'20005,487,133'Distance calculating neural network classifier chip and system'19965,268,320'Method of increasing the accuracy of an analog circuit employing floating gate memory devices'19935,264,734'Difference calculating neural network utilizing switched capacitors'19935,256,911'Neural network with multiplexed snyaptic processing'19935,146,602'Method of increasing the accuracy of an analog neural network and the like'19925,087,826'Multi-layer neural network employing multiplexed output neurons'19925,077,230'Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth'19915,075,869'Neural network exhibiting improved tolerance to temperature and power supply variations'19915,075,245'Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps'19915,055,897'Semiconductor cell for neural network and the like'19915,028,810'Four quadrant synapse cell employing single column summing line'19914,961,002'Synapse cell employing dual gate transistor structure'19904,956,564'Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network'19904,950,917'Semiconductor cell for neural network employing a four-quadrant multiplier'19904,906,865'Sample and hold circuit for temporal associations in a neural network'19904,784,965'Source drain doping technique'19884,780,424'Process for fabricating electrically alterable floating gate memory devices'19884,757,026'Source drain doping technique'19884,728,617'Method of fabricating a MOSFET with graded source and drain regions'19884,519,849'Method of making EPROM cell with reduced programming voltage'19854,460,981'Virtual ground memory'19844,412,310'EPROM Cell with reduced programming voltage and method of fabrication'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–2006Patents assigned to INTEL CORP (26)· patent assignee history
1983–1985Based in Milpitas, CA, US· patent location history
1988–2006Based in Palo Alto, CA, US· patent location history
2000Based in Jones Creek, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 1983–2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 23 | 1988–2006 |
| Milpitas, California, US | 3 | 1983–1985 |
| Jones Creek, Texas, US | 1 | 2000 |