Inventor
Glenn D. Gilda
Inventor
Binghamton, NY, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
G11CStatic stores25%
H03MCoding4%
H04LTransmission of digital information, e.g. telegraphic communication4%
G01KMeasuring temperature2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
10,833,707Error trapping in memory structures202010,684,968Conditional memory spreading for heterogeneous memory sizes202010,601,448Reduced latency error correction decoding202010,558,519Power-reduced redundant array of independent memory (RAIM) system202010,296,417Reducing uncorrectable errors based on a history of correctable errors201910,254,961Dynamic load based memory tag management201910,055,287Reducing uncorrectable errors based on a history of correctable errors20189,946,595Reducing uncorrectable errors based on a history of correctable errors20189,594,646'Reestablishing synchronization in a memory system'20179,594,647'Synchronization and order detection in a memory system'20179,563,548'Error injection and error counting during memory scrubbing operations'20179,535,778'Reestablishing synchronization in a memory system'20179,495,231'Reestablishing synchronization in a memory system'20169,495,254'Synchronization and order detection in a memory system'20169,459,997'Error injection and error counting during memory scrubbing operations'20169,430,418'Synchronization and order detection in a memory system'20169,318,171'Dual asynchronous and synchronous memory system'20169,146,864'Address mapping including generic bits for universal addressing independent of memory type'20159,142,272'Dual asynchronous and synchronous memory system'20159,136,987'Replay suspension in a memory system'20159,104,564'Early data delivery prior to error detection completion'20159,092,330'Early data delivery prior to error detection completion'20159,037,811'Tagging in memory control unit (MCU)'20157,934,046'Access table lookup for bus bridge'20116,973,528'Data caching on bridge following disconnect'20056,920,519'System and method for supporting access to multiple I/O hub nodes in a host bridge'20056,785,759'System and method for sharing I/O address translation caching across multiple host bridges'20046,490,660'Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system'20026,438,657'Pipelined snooping of multiple L1 cache lines'20026,138,206'Data register for multicycle data cache read'20006,115,795'Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system'20006,065,101'Pipelined snooping of multiple L1 cache lines'20005,454,093'Buffer bypass for quick data access'19954,964,737'Removable thermocouple template for monitoring temperature of multichip modules'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2020Patents assigned to IBM (34)· patent assignee history
1990–1995Based in Endicott, NY, US· patent location history
2000–2020Based in Binghamton, NY, US· patent location history
2017Based in Binghampton, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 34 | 1990–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Binghamton, New York, US | 31 | 2000–2020 |
| Endicott, New York, US | 2 | 1990–1995 |
| Binghampton, New York, US | 1 | 2017 |