Inventor

Sung-Mo Kang

Inventor
Santa Cruz, CA, US

Overview

23→
Patents
1995–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique44%
H10DInorganic electric semiconductor devices13%
G11CStatic stores9%
G01RMeasuring electric variables6%
G06FElectric digital data processing6%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
H01HElectric switches3%
H04JMultiplex communication3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H05KPrinted circuits3%
PatentTitleYear
11,013,114Printed circuit board20217,701,235'Substrate test probing equipment having forcing part for test head and force-receiving pattern for probe card and methods of using the same'20107,466,191'Self reverse bias low-power high-performance storage circuitry and related methods'20087,190,209'Low-power high-performance integrated circuit and related methods'20076,992,915'Self reverse bias low-power high-performance storage circuitry and related methods'20066,977,528'Event driven dynamic logic for reducing power consumption'20056,946,901'Low-power high-performance integrated circuit and related methods'20056,900,690'Low-power high-performance integrated circuit and related methods'20056,888,202'Low-power high-performance storage circuitry'20056,861,911'Self-regulating voltage controlled oscillator'20056,794,903'CMOS parallel dynamic logic and speed enhanced static logic'20046,787,725'Switching mechanism of circuit breaker for gas insulted switchgear'20046,784,694'CMOS sequential logic configuration for an edge triggered flip-flop'20046,784,707'Delay locked loop clock generator'20046,759,873'Reverse biasing logic circuit'20046,642,729'Probe card for tester head'20036,624,665'CMOS skewed static logic and method of synthesis'20035,923,656'Scalable broad band input-queued ATM switch including weight driven cell scheduler'19995,796,638'Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein'19985,610,744'Optical communications and interconnection networks having opto-electronic switches and direct optical routers'19975,468,667'Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit'19955,450,267'ESD/EOS protection circuits for integrated circuits'19955,404,041'Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–1998Patents assigned to TEXAS INSTRUMENTS INC (4)· patent assignee history
1995–1999Based in Champaign, IL, US· patent location history
1997–2004Patents assigned to UNIV ILLINOIS (8)· patent assignee history
1998Patents assigned to HEWLETT PACKARD CO (1)· patent assignee history
2003–2010Patents assigned to SAMSUNG ELECTRONICS CO LTD (2)· patent assignee history
2003–2008Based in Santa Cruz, CA, US· patent location history
2003–2021Based in Suwon-si, KR· patent location history
2004Based in Cheongju, KR· patent location history
2005–2008Patents assigned to UNIV CALIFORNIA (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
UNIV ILLINOIS81997–2004
UNIV CALIFORNIA72005–2008
TEXAS INSTRUMENTS INC41995–1998
SAMSUNG ELECTRONICS CO LTD22003–2010
HEWLETT PACKARD CO11998
Locations
LocationPatentsSpan
Santa Cruz, California, US132003–2008
Champaign, Illinois, US61995–1999
Suwon-si, KR32003–2021
Cheongju, KR12004