LexDanaLexDanabeta
Inventor

Deepak C. Sekar

Inventor
San Jose, CA, US

Overview

165→
Patents
2008–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 165 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10DInorganic electric semiconductor devices16%
H10BElectronic memory devices14%
H01LSemiconductor devices12%
G11CStatic stores11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10NElectric solid-state devices not otherwise provided for7%
B82YSpecific uses or applications of nanostructures2%
H03KPulse technique2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
PatentTitleYear
11,133,3513D semiconductor device and structure202111,133,344Multilevel semiconductor device and structure with image sensors202111,121,0213D semiconductor device and structure202111,109,716Enhanced automated food making apparatus202111,107,7213D semiconductor device and structure with NAND logic202111,101,2663D device and devices with bonding202111,094,576Methods for producing a 3D semiconductor memory device and structure202111,088,0503D semiconductor device with isolation layers202111,087,9953D semiconductor device and structure202111,081,1762T-1R architecture for resistive RAM202111,063,071Multilevel semiconductor device and structure with waveguides202110,833,1083D microdisplay device and structure202010,825,518Fast read speed memory device202010,825,8643D semiconductor device and structure202010,813,503Automated food making apparatus202010,783,9641T-1R architecture for resistive random access memory202010,679,9773D microdisplay device and structure202010,665,6953D semiconductor device with isolation layers202010,658,037Reduced current memory device202010,651,0543D semiconductor device and structure202010,622,0622T-1R architecture for resistive ram202010,600,8883D semiconductor device202010,600,6573D semiconductor device and structure202010,497,7133D semiconductor memory device and structure201910,388,8633D memory device and structure201910,388,3721T-1R architecture for resistive random access memory201910,388,375Fast read speed memory device201910,388,5683D semiconductor device and system201910,366,9703D semiconductor device and structure201910,354,995Semiconductor memory device and structure201910,325,6513D semiconductor device with stacked memory201910,290,6823D IC semiconductor device and structure with stacked memory201910,224,100Reduced current memory device201910,217,6673D semiconductor device, fabrication method and system201910,199,0982T-1R architecture for resistive RAM201910,157,9093D semiconductor device and structure201810,115,6633D semiconductor device and structure201810,043,7813D semiconductor device and structure201810,038,0733D integrated circuit device201810,037,8012T-1R architecture for resistive RAM201810,037,691Behavioral based traffic infraction detection and analysis system20189,953,8703D semiconductor device and system20189,953,972Semiconductor system, device and structure20189,953,925Semiconductor system and device20189,954,0803D integrated circuit device20189,941,005Fast read speed memory device20189,941,319Semiconductor and optoelectronic methods and devices20189,941,332Semiconductor memory device and structure20189,941,2753D semiconductor device and structure20189,911,627'Method of processing a semiconductor device'20189,892,972'3D semiconductor device and structure'20189,860,329'Determining customized audio services'20189,853,089Semiconductor device and structure20179,824,752'1T-1R architecture for resistive random access memory'20179,818,800'Self aligned semiconductor device and structure'2017RE046498'Reducing energy consumption when applying body bias to substrate having sets of NAND strings'20179,711,407'Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer'20179,691,869'Semiconductor devices and structures'20179,613,844'3D semiconductor device having two layers of transistors'20179,613,887'Semiconductor system, device and structure'20179,570,165'1D-2R memory architecture'20179,564,432'3D semiconductor device and structure'20179,490,009'Fast read speed memory device'20169,460,991'Semiconductor device and structure'20169,460,978'Semiconductor device and structure'20169,419,031'Semiconductor and optoelectronic devices'20169,406,670'System comprising a semiconductor device and structure'20169,390,798'1T-1R architecture for resistive random access memory'20169,385,058'Semiconductor device and structure'20169,385,088'3D semiconductor device and structure'20169,305,867'Semiconductor devices and structures'20169,299,641'Semiconductor system, device and structure with heat removal'20169,230,641'Fast read speed memory device'20169,219,005'Semiconductor system and device'20159,197,804'Semiconductor and optoelectronic devices'20159,136,153'3D semiconductor device and structure with back-bias'20159,099,424'Semiconductor system, device and structure with heat removal'20159,099,526'Integrated circuit device and structure'20159,087,572'Content addressable memory'20159,034,689'Non-volatile storage with metal oxide switching element and methods for fabricating the same'20159,030,858'Semiconductor device and structure'20159,029,173'Method for fabrication of a semiconductor device and structure'20159,000,557'Semiconductor device and structure'20158,987,046'Trap passivation in memory cell with metal oxide switching element'20158,975,670'Semiconductor device and structure for heat removal'20158,956,959'Method of manufacturing a semiconductor device with two monocrystalline layers'20158,907,442'System comprising a semiconductor device and structure'20148,901,613'Semiconductor device and structure for heat removal'20148,836,073'Semiconductor device and structure'20148,823,122'Semiconductor and optoelectronic devices'20148,803,206'3D semiconductor device and structure'20148,772,749'Bottom electrodes for use with metal oxide resistivity switching layers'20148,754,533'Monolithic three-dimensional semiconductor device and structure'20148,753,913'Method for fabricating novel semiconductor and optoelectronic devices'20148,742,476'Semiconductor device and structure'20148,709,880'Method for fabrication of a semiconductor device and structure'20148,703,597'Method for fabrication of a semiconductor device and structure'20148,686,419'Structure and fabrication method for resistance-change memory cell in 3-D memory'20148,686,428'Semiconductor device and structure'20148,687,399'Semiconductor device and structure'20148,664,042'Method for fabrication of configurable systems'20148,642,416'Method of forming three dimensional integrated circuit devices using layer transfer technique'20148,637,845'Optimized electrodes for Re-RAM'20148,581,349'3D memory semiconductor device and structure'20138,575,715'Punch-through diode steering element'20138,574,929'Method to form a 3D semiconductor device and structure'20138,557,632'Method for fabrication of a semiconductor device and structure'20138,541,819'Semiconductor device and structure'20138,536,023'Method of manufacturing a semiconductor device and structure'20138,498,146'Programming reversible resistance switching elements'20138,487,292'Resistance-switching memory cell with heavily doped metal oxide layer'20138,476,145'Method of fabricating a semiconductor device and structure'20138,461,035'Method for fabrication of a semiconductor device and structure'20138,450,804'Semiconductor device and structure for heat removal'20138,440,542'Semiconductor device and structure'20138,435,831'Non-volatile storage with metal oxide switching element and methods for fabricating the same'20138,405,420'System comprising a semiconductor device and structure'20138,395,191'Semiconductor device and structure'20138,379,458'Semiconductor device and structure'20138,378,494'Method for fabrication of a semiconductor device and structure'20138,373,230'Method for fabrication of a semiconductor device and structure'20138,362,482'Semiconductor device and structure'20138,354,660'Bottom electrodes for use with metal oxide resistivity switching layers'20138,298,875'Method for fabrication of a semiconductor device and structure'20128,294,159'Method for fabrication of a semiconductor device and structure'20128,283,215'Semiconductor and optoelectronic devices'20128,274,130'Punch-through diode steering element'20128,273,610'Method of constructing a semiconductor device and structure'20128,237,228'System comprising a semiconductor device and structure'20128,216,862'Forming and training processes for resistance-change memory cell'20128,203,148'Semiconductor device and structure'20128,164,957'Reducing energy consumption when applying body bias to substrate having sets of nand strings'20128,163,581'Semiconductor and optoelectronic devices'20128,153,499'Method for fabrication of a semiconductor device and structure'20128,154,904'Programming reversible resistance switching elements'20128,148,728'Method for fabrication of a semiconductor device and structure'20128,114,757'Semiconductor device and structure'20128,058,137'Method for fabrication of a semiconductor device and structure'20118,026,521'Semiconductor device and structure'20118,000,146'Applying different body bias to different substrate portions for non-volatile storage'20117,986,042'Method for fabrication of a semiconductor device and structure'20117,969,011'MIIM diodes having stacked structure'20117,964,916'Method for fabrication of a semiconductor device and structure'20117,960,242'Method for fabrication of a semiconductor device and structure'20117,935,594'Damascene process for carbon memory element with MIIM diode'20117,928,563'3-D ICs with microfluidic interconnects and methods of constructing same'20117,897,453'Dual insulating layer diode with asymmetric interface state and method of fabrication'20117,764,547'Regulation of source potential to combat cell source IR drop'20107,751,244'Applying adaptive body bias to non-volatile storage based on number of programming cycles'20107,615,439'Damascene process for carbon memory element with MIIM diode'20097,606,072'Non-volatile storage with compensation for source voltage drop'20097,606,071'Compensating source voltage drop in non-volatile storage'20097,606,079'Reducing power consumption during read operations in non-volatile storage'20097,583,539'Non-volatile storage with bias for temperature compensation'20097,583,535'Biasing non-volatile storage to compensate for temperature variations'20097,577,031'Non-volatile memory with compensation for variations along a word line'20097,554,853'Non-volatile storage with bias based on selective word line'20097,551,477'Multiple bit line voltages based on distance'20097,532,516'Non-volatile storage with current sensing of negative threshold voltages'20097,525,843'Non-volatile storage with adaptive body bias'20097,508,713'Method of compensating variations along a word line in a non-volatile memory'20097,468,919'Biasing non-volatile storage based on selected word line'20087,468,920'Applying adaptive body bias to non-volatile storage'20087,447,079'Method for sensing negative threshold voltages in non-volatile storage using current sensing'20087,440,327'Non-volatile storage with reduced power consumption during read operations'2008

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2010Patents assigned to SANDISK CORP (18)· patent assignee history
2008–2011Based in Atlanta, GA, US· patent location history
2008–2017Based in Mountain View, CA, US· patent location history
2009–2021Based in Sunnyvale, CA, US· patent location history
2011–2021Patents assigned to MONOLITHIC 3D INC (103)· patent assignee history
2011–2017Patents assigned to SEKAR DEEPAK C (49)· patent assignee history
2011–2017Patents assigned to OR-BACH ZVI (42)· patent assignee history
2011–2017Patents assigned to CRONQUIST BRIAN (31)· patent assignee history
2011–2021Based in San Jose, CA, US· patent location history
2018Based in Mount Lawley, AU· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MONOLITHIC 3D INC1032011–2021
SEKAR DEEPAK Cself492011–2017
OR-BACH ZVI422011–2017
CRONQUIST BRIAN312011–2017
SANDISK CORP182008–2010
Locations
LocationPatentsSpan
San Jose, California, US1212011–2021
Sunnyvale, California, US212009–2021
Atlanta, Georgia, US112008–2011
Mountain View, California, US102008–2017
Mount Lawley, AU12018