Inventor
Krishna Vijaya Chakravadhanula
Inventor
Vestal, NY, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables52%
G06FElectric digital data processing36%
G11CStatic stores6%
G06NComputing arrangements based on specific computational models3%
H03KPulse technique3%
PatentTitleYear
10,996,270System and method for multiple device diagnostics and failure grouping202110,955,470Method to improve testability using 2-dimensional exclusive or (XOR) grids202110,853,100Systems and methods for creating learning-based personalized user interfaces202010,775,435Low-power shift with clock staggering202010,761,131Method for optimally connecting scan segments in two-dimensional compression chains202010,551,4352D compression-based low power ATPG202010,528,689Verification process for IJTAG based test pattern migration202010,331,506SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores201910,325,048Virtual directory navigation and debugging across multiple test configurations in the same session20199,817,068'Method and system for improving efficiency of sequential test compression using overscan'20179,817,069'Method and system for construction of a highly efficient and predictable sequential test decompression logic'20179,606,179'Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer'20179,513,335'Method for using XOR trees for physically efficient scan compression and decompression logic'20169,470,756'Method for using sequential decompression logic for VLSI test in a physically efficient construction'20169,470,754'Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization'20169,470,755'Method for dividing testable logic into a two-dimensional grid for physically efficient scan'20169,170,301'Hierarchical compaction for test pattern power generation'20158,904,256'Method and apparatus for low-pin count testing of integrated circuits'20148,650,524'Method and apparatus for low-pin count testing of integrated circuits'20148,615,692'Method and system for analyzing test vectors to determine toggle counts'20138,296,694'System and method for automated synthesis of circuit wrappers'20128,296,703'Fault modeling for state retention logic'20128,271,226'Testing state retention logic in low power systems'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2021Patents assigned to CADENCE DESIGN SYSTEMS INC (23)· patent assignee history
2012–2013Patents assigned to CHICKERMANE VIVEK (4)· patent assignee history
2012–2013Patents assigned to CHAKRAVADHANULA KRISHNA (3)· patent assignee history
2012Patents assigned to GREGOR STEVEN L (2)· patent assignee history
2012–2021Based in Vestal, NY, US· patent location history
2019–2020Patents assigned to CADENCE DESIGNS SYSTEMS INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 23 | 2012–2021 |
| CHICKERMANE VIVEK | 4 | 2012–2013 |
| CHAKRAVADHANULA KRISHNAself | 3 | 2012–2013 |
| CADENCE DESIGNS SYSTEMS INC | 2 | 2019–2020 |
| GREGOR STEVEN L | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Vestal, New York, US | 23 | 2012–2021 |