Inventor
Craig T. Salling
Inventor
Plano, TX, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
G11CStatic stores29%
H10BElectronic memory devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
7,256,460'Body-biased pMOS protection against electrostatic discharge'20077,253,464'Junction-isolated depletion mode ferroelectric memory devices and systems'20077,236,387'Writing to ferroelectric memory devices'20077,199,413'Junction-isolated depletion mode ferroelectric memory devices and systems'20077,187,530'Electrostatic discharge protection circuit'20077,123,503'Writing to ferroelectric memory devices'20067,002,198'Junction-isolated depletion mode ferroelectric memory devices'20066,982,449'Junction-isolated depletion mode ferroelectric memory devices'20066,944,043'Junction-isolated depletion mode ferroelectric memory devices'20056,937,501'Writing to ferroelectric memory devices'20056,903,960'Junction-isolated depletion mode ferroelectric memory devices'20056,900,969'ESD protection with uniform substrate bias'20056,888,738'Methods of writing junction-isolated depletion mode ferroelectric memory devices'20056,888,185'Junction-isolated depletion mode ferroelectric memory devices'20056,888,747'Methods of reading junction-isolated depletion mode ferroelectric memory devices'20056,882,560'Reading ferroelectric memory cells'20056,875,650'Eliminating substrate noise by an electrically isolated high-voltage I/O transistor'20056,876,022'Junction-isolated depletion mode ferroelectric memory devices'20056,858,902'Efficient ESD protection with application for low capacitance I/O pads'20056,835,623'NMOS ESD protection device with thin silicide and methods for making same'20046,791,862'Junction-isolated depletion mode ferroelectric memory devices'20046,767,810'Method to increase substrate potential in MOS transistors used in ESD protection circuits'20046,764,909'Structure and method of MOS transistor having increased substrate resistance'20046,724,050'ESD improvement by a vertical bipolar transistor with low breakdown voltage and high beta'20046,665,206'Array architecture for depletion mode ferroelectric memory devices'20036,646,906'Methods of reading ferroelectric memory cells'20036,627,955'Structure and method of MOS transistor having increased substrate resistance'20036,587,365'Array architecture for depletion mode ferroelectric memory devices'20036,574,131'Depletion mode ferroelectric memory device and method of writing to and reading from the same'20036,563,175'NMOS ESD protection device with thin silicide and methods for making same'20036,522,571'Methods of forming and reading ferroelectric memory cells'20036,515,889'Junction-isolated depletion mode ferroelectric memory'20036,449,187'Method and apparatus for programming flash memory device'20026,366,489'Bi-state ferroelectric memory devices, uses and operation'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2007Patents assigned to MICRON TECHNOLOGY INC (22)· patent assignee history
2002–2007Patents assigned to TEXAS INSTRUMENTS INC (11)· patent assignee history
2002–2007Based in Plano, TX, US· patent location history
2005–2007Based in Cupertino, CA, US· patent location history
2005Based in Chatsworth, TX, US· patent location history
2007Patents assigned to T RAM SEMICONDUCTOR INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 22 | 2002–2007 |
| TEXAS INSTRUMENTS INC | 11 | 2002–2007 |
| T RAM SEMICONDUCTOR INC | 1 | 2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 30 | 2002–2007 |
| Cupertino, California, US | 3 | 2005–2007 |
| Chatsworth, Texas, US | 1 | 2005 |