Inventor
Jae Ouk Choo
Inventor
Chandler, AZ, US
Overview
Patents· 12 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H01LSemiconductor devices12%
B24BMachines, devices, or processes for grinding or polishing10%
C09GPolishing compositions10%
C09KMaterials for miscellaneous applications, not provided for elsewhere10%
C01FCompounds of the metals beryllium, magnesium, aluminium, calcium, strontium, barium, radium, thorium, or of the rare-earth metals7%
C01PIndexing scheme relating to structural and physical aspects of solid inorganic compounds7%
G09GArrangements or circuits for control of indicating devices using static means to present variable information7%
H10DInorganic electric semiconductor devices5%
PatentTitleYear
10,566,231Interconnect formation with chamferless via, and related interconnect202010,011,741Chemical mechanical polishing (CMP) composition for shallow trench isolation (STI) applications and methods of making thereof20189,305,806'Chemical mechanical polishing slurry compositions and method using the same for copper and through-silicon via applications'20169,305,476'Chemical mechanical polishing (CMP) composition for shallow trench isolation (STI) applications and methods of making thereof'20169,062,230'Chemical mechanical polishing (CMP) composition for shallow trench isolation (STI) applications and methods of making thereof'20158,974,692'Chemical mechanical polishing slurry compositions and method using the same for copper and through-silicon via applications'20158,859,428'Chemical mechanical polishing (CMP) composition for shallow trench isolation (STI) applications and methods of making thereof'20147,902,609'Semiconductor devices including multiple stress films in interface area'20117,785,951'Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby'20107,642,148'Methods of producing semiconductor devices including multiple stress films in interface area'20107,595,253'Method of forming the semiconductor device'20097,452,817'CMP method providing reduced thickness variations'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2011Patents assigned to SAMSUNG ELECTRONICS CO LTD (5)· patent assignee history
2008–2010Based in Gyeonggi-do, KR· patent location history
2009–2011Based in Yongin-si, KR· patent location history
2014–2018Patents assigned to AIR PROD & CHEM (6)· patent assignee history
2014–2018Based in Chandler, AZ, US· patent location history
2018Patents assigned to VERSUM MAT US LLC (1)· patent assignee history
2020Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
2020Based in Clifton Park, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AIR PROD & CHEM | 6 | 2014–2018 |
| SAMSUNG ELECTRONICS CO LTD | 5 | 2008–2011 |
| GLOBALFOUNDRIES INC | 1 | 2020 |
| VERSUM MAT US LLC | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chandler, AZ, US | 6 | 2014–2018 |
| Yongin-si, KR | 3 | 2009–2011 |
| Gyeonggi-do, KR | 2 | 2008–2010 |
| Clifton Park, New York, US | 1 | 2020 |