Inventor
Chun Yan
Inventor
San Jose, CA, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1034%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices10%
H01JElectric discharge tubes or discharge lamps7%
B08BCleaning in general6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
C23CCoating metallic material4%
H10NElectric solid-state devices not otherwise provided for3%
C23FNon-mechanical removal of metallic material from surface2%
B24CAbrasive or related blasting with particulate material1%
PatentTitleYear
10,504,717Integrated system and method for source/drain engineering201910,438,796Method for removing native oxide and residue from a III-V group containing surface201910,332,739UV radiation system and method for arsenic outgassing control in sub 7nm CMOS fabrication201910,243,063Method of uniform channel formation201910,236,190Method for wafer outgassing control201910,224,421Self-aligned process for sub-10nm fin formation201910,205,002Method of epitaxial growth shape control for CMOS applications201910,177,017Method for conditioning a processing chamber for steady etching rate control201910,147,596Methods and solutions for cleaning INGAAS (or III-V) substrates201810,115,607Method and apparatus for wafer outgassing control201810,090,147Integrated system and method for source/drain engineering201810,043,667Integrated method for wafer outgassing reduction201810,002,759Method of forming structures with V shaped bottom on silicon substrate20189,905,412'Method and solution for cleaning InGaAs (or III-V) substrates'20189,865,706'Integrated process and structure to form III-V channel for sub-7nm CMOS devices'20189,852,903System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET20179,805,914'Methods for removing contamination from surfaces in substrate processing systems'20179,653,291'Method for removing native oxide and residue from a III-V group containing surface'20179,653,282'Silicon-containing substrate cleaning procedure'20179,484,220'Sputter etch processing for heavy metal patterning in integrated circuits'20169,472,416'Methods of surface interface engineering'20169,114,438'Copper residue chamber clean'20158,871,107'Subtractive plasma etching of a blanket layer of metal or metal alloy'20147,442,114'Methods for silicon electrode assembly etch rate and etch uniformity recovery'20087,374,636'Method and apparatus for providing uniform plasma in a magnetic field enhanced plasma reactor'20087,320,942'Method for removal of metallic residue after plasma etching of a metal layer'20087,316,199'Method and apparatus for controlling the magnetic field intensity in a plasma enhanced semiconductor wafer processing chamber'20086,933,239'Method for removing conductive residue'20056,841,484'Method of fabricating a magneto-resistive random access memory (MRAM) device'20056,784,107'Method for planarizing a copper interconnect structure'20046,649,532'Methods for etching an organic anti-reflective coating'20036,620,289'Method and apparatus for asymmetric gas distribution in a semiconductor wafer processing system'20036,547,977'Method for etching low k dielectrics'20036,537,918'Method for etching silicon oxynitride and dielectric antireflection coatings'20036,458,516'Method of etching dielectric layers using a removable hardmask'20026,352,049'Plasma assisted processing chamber with separate control of species density'20026,331,380'Method of pattern etching a low K dielectric layer'20016,296,780'System and method for etching organic anti-reflective coating from a substrate'20016,291,356'Method for etching silicon oxynitride and dielectric antireflection coatings'20016,080,529'Method of etching patterned layers useful as masking during subsequent etching or for damascene structures'2000D0324995'Dual bottle unit'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992Patents assigned to SPORTTLER LTD (1)· patent assignee history
1992Based in Kowloon, HK· patent location history
2000–2019Patents assigned to APPLIED MATERIALS INC (36)· patent assignee history
2000–2003Based in Santa Clara, CA, US· patent location history
2003–2019Based in San Jose, CA, US· patent location history
2008Patents assigned to LAM RES CORP (1)· patent assignee history
2014–2016Patents assigned to IBM (3)· patent assignee history
2016Patents assigned to APPLIED MAT INCORPORATED (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 36 | 2000–2019 |
| IBM | 3 | 2014–2016 |
| APPLIED MAT INCORPORATED | 1 | 2016 |
| LAM RES CORP | 1 | 2008 |
| SPORTTLER LTD | 1 | 1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 31 | 2003–2019 |
| Santa Clara, California, US | 9 | 2000–2003 |
| Kowloon, HK | 1 | 1992 |