Inventor
Stephen P. Ayotte
Inventor
Bristol, VT, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H01LSemiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
G01RMeasuring electric variables9%
B23KSoldering or unsoldering6%
G01NInvestigating or analysing materials by determining their chemical or physical properties5%
G01LMeasuring force, stress, torque, work, mechanical power, mechanical efficiency, or fluid pressure3%
H03KPulse technique3%
H05KPrinted circuits3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
11,075,619Contactless readable programmable transponder to monitor chip join202110,605,850Screening methodology to eliminate wire sweep in bond and assembly module packaging202010,601,404Contactless readable programmable transponder to monitor chip join202010,429,414Multiple contact probe head disassembly method and system201910,309,884Predicting semiconductor package warpage201910,256,204Separation of integrated circuit structure from adjacent chip201910,245,667Chip joining by induction heating201910,200,016Contactless readable programmable transponder to monitor chip join201910,050,012Method for semiconductor die removal rework20189,876,487Contactless readable programmable transponder to monitor chip join20189,776,270'Chip joining by induction heating'20179,772,268'Predicting semiconductor package warpage'20179,711,422'Visually detecting electrostatic discharge events'20179,704,830'Semiconductor structure and method of making'20179,645,573'Reliability monitor test strategy definition'20179,548,275'Detecting sudden changes in acceleration in semiconductor device or semiconductor packaging containing semiconductor device'20179,508,680'Induction heating for underfill removal and chip rework'20169,470,740'Screening methodology to eliminate wire sweep in bond and assembly module packaging'20169,472,490'IC structure with recessed solder bump area and methods of forming same'20169,230,921'Self-healing crack stop structure'20169,222,707'Temperature stabilization in semiconductors using the magnetocaloric effect'20159,190,375'Solder bump reflow by induction heating'20159,177,931'Reducing thermal energy transfer during chip-join processing'20159,105,573'Visually detecting electrostatic discharge events'20159,059,097'Inhibiting propagation of imperfections in semiconductor devices'20158,987,010'Microprocessor image correction and method for the detection of potential defects'20158,829,674'Stacked multi-chip package and method of making same'20148,765,593'Controlled collapse chip connection (C4) structure and methods of forming'20148,453,843'Tray for transporting semiconductor devices of a BGA type'20138,426,856'Thermally sensitive material embedded in the substrate'20138,230,903'Low profile heat sink for semiconductor devices'20128,207,609'Optically transparent wires for secure circuits and methods of making same'20128,017,514'Optically transparent wires for secure circuits and methods of making same'20117,939,390'Gap capacitors for monitoring stress in solder balls in flip chip technology'20117,915,732'Production of integrated circuit chip packages prohibiting formation of micro solder balls'20117,839,002'Partially underfilled solder grid arrays'20107,745,256'Rectangular-shaped controlled collapse chip connection'20107,709,876'Gap capacitors for monitoring stress in solder balls in flip chip technology'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2021Patents assigned to IBM (29)· patent assignee history
2010–2019Based in Bristol, VT, US· patent location history
2012–2015Patents assigned to SULLIVAN TIMOTHY M (6)· patent assignee history
2012–2015Patents assigned to AYOTTE STEPHEN P (5)· patent assignee history
2012–2015Patents assigned to HILL DAVID J (4)· patent assignee history
2013Based in Burlington, VT, US· patent location history
2014Based in Briston, VT, US· patent location history
2015–2019Patents assigned to GLOBALFOUNDRIES INC (11)· patent assignee history
2015–2020Based in Essex Junction, VT, US· patent location history
2016–2021Based in New Haven, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 29 | 2010–2021 |
| GLOBALFOUNDRIES INC | 11 | 2015–2019 |
| SULLIVAN TIMOTHY M | 6 | 2012–2015 |
| AYOTTE STEPHEN Pself | 5 | 2012–2015 |
| HILL DAVID J | 4 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bristol, VT, US | 25 | 2010–2019 |
| New Haven, VT, US | 6 | 2016–2021 |
| Essex Junction, VT, US | 4 | 2015–2020 |
| Burlington, VT, US | 2 | 2013 |
| Briston, VT, US | 1 | 2014 |