Inventor
Wei-Yuan Lu
Inventor
Taipei, TW
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H01LSemiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10BElectronic memory devices4%
B82YSpecific uses or applications of nanostructures2%
H05KPrinted circuits2%
PatentTitleYear
10,868,149Source and drain surface treatment for multi-gate field effect transistors202010,840,243Semiconductor device and manufacturing method thereof202010,741,642Formation of dislocations in source and drain regions of finFET devices202010,727,340Strained structure of a semiconductor device202010,529,803Semiconductor device with epitaxial source/drain202010,522,424FinFET doping methods and structures thereof201910,510,762Source and drain formation technique for fin-like field effect transistor201910,446,669Source and drain surface treatment for multi-gate field effect transistors201910,325,911Semiconductor device and manufacturing method thereof201910,269,967MOSFETs with multiple dislocation planes201910,153,344Formation of dislocations in source and drain regions of FinFET devices20189,853,157MOSFETs with multiple dislocation planes20179,768,256'Formation of dislocations in source and drain regions of FinFET devices'20179,698,054'Strained structure of a p-type field effect transistor'20179,685,534'Method for semiconductor device fabrication'20179,583,342'FinFET doping methods and structures thereof'20179,431,404'Techniques providing high-k dielectric metal gate CMOS'20169,356,136'Engineered source/drain region for n-Type MOSFET'20169,299,838'MOSFETs with multiple dislocation planes'20169,299,803'Method for semiconductor device fabrication'20169,293,534'Formation of dislocations in source and drain regions of FinFET devices'20169,178,063'Semiconductor device'20159,099,346'Techniques providing high-k dielectric metal gate CMOS'20158,952,459'Gate structure having lightly doped region'20158,828,817'Semiconductor device and method of forming the same'20148,815,722'Methods of forming integrated circuits'20148,809,918'MOSFETs with multiple dislocation planes'20148,754,477'Semiconductor device with multiple stress structures and method of forming the same'20148,580,641'Techniques providing high-k dielectric metal gate CMOS'20138,535,998'Method for fabricating a gate structure'20138,502,316'Self-aligned two-step STI formation through dummy poly removal'20138,368,147'Strained semiconductor device with recessed channel'20138,053,344'Methods of forming integrated circuits'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (15)· patent assignee history
2011–2020Based in Taipei, TW· patent location history
2013–2017Patents assigned to LU WEI-YUAN (9)· patent assignee history
2013–2014Patents assigned to TSAI HAN-TING (7)· patent assignee history
2013–2014Patents assigned to CHEN KUAN-CHUNG (5)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 18 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 15 | 2011–2016 |
| LU WEI-YUANself | 9 | 2013–2017 |
| TSAI HAN-TING | 7 | 2013–2014 |
| CHEN KUAN-CHUNG | 5 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 33 | 2011–2020 |