Inventor
Scott Whitney Gould
Inventor
South Burlington, VT, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
H03KPulse technique26%
G11CStatic stores11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G01RMeasuring electric variables4%
H10DInorganic electric semiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
7,961,932'Method and apparatus for manufacturing diamond shaped chips'20117,496,877'Electrostatic discharge failure avoidance through interaction between floorplanning and power routing'20097,289,659'Method and apparatus for manufacturing diamond shaped chips'20077,234,124'Method and apparatus for performing power routing on a voltage island within an integrated circuit chip'20077,131,074'Nested voltage island architecture'20067,096,436'Macro design techniques to accommodate chip level wiring and circuit placement across the macro'20066,917,430'Method to improve the control of source chemicals delivery by a carrier gas'20056,883,152'Voltage island chip implementation'20056,883,155'Macro design techniques to accommodate chip level wiring and circuit placement across the macro'20056,861,753'Method and apparatus for performing power routing on a voltage island within an integrated circuit chip'20056,832,361'System and method for analyzing power distribution using static timing analysis'20046,825,711'Power reduction by stage in integrated circuit'20046,820,240'Voltage island chip implementation'20046,802,033'Low-power critical error rate communications controller'20046,779,163'Voltage island design planning'20046,731,154'Global voltage buffer for voltage islands'20046,598,206'Method and system of modifying integrated circuit power rails'20036,543,040'Macro design techniques to accommodate chip level wiring and circuit placement across the macro'20036,493,859'Method of wiring power service terminals to a power network in a semiconductor integrated circuit'20026,490,708'Method of integrated circuit design by selection of noise tolerant gates'20026,425,092'Method and apparatus for preventing thermal failure in a semiconductor device through redundancy'20026,397,170'Simulation based power optimization'20026,345,362'Managing Vt for reduced power using a status table'20026,237,132'Toggle based application specific core methodology'20016,233,191'Field programmable memory array'20016,134,704'Integrated circuit macro apparatus'20006,130,854'Programmable address decoder for field programmable memory array'20006,118,707'Method of operating a field programmable memory array with a field programmable gate array'20006,075,745'Field programmable memory array'20006,023,421'Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array'20006,021,513'Testable programmable gate array and associated LSSD/deterministic test methodology'20005,949,719'Field programmable memory array'19995,910,733'Method and system for layout and schematic generation for heterogeneous arrays'19995,867,507'Testable programmable gate array and associated LSSD/deterministic test methodology'19995,781,032'Programmable inverter circuit used in a programmable logic cell'19985,761,078'Field programmable gate arrays using semi-hard multicell macros'19985,760,611'Function generator for programmable gate array'19985,748,009'Programmable logic cell'19985,745,734'Method and system for programming a gate array using a compressed configuration bit stream'19985,734,582'Method and system for layout and schematic generation for heterogeneous arrays'19985,732,246'Programmable array interconnect latch'19985,717,346'Low skew multiplexer network and programmable array clock/reset application thereof'19985,703,498'Programmable array clock/reset resource'19975,694,057'System for enhanced drive in programmable gate arrays'19975,671,432'Programmable array I/O-routing resource'19975,652,529'Programmable array clock/reset resource'19975,646,546'Programmable logic cell having configurable gates and multiplexers'19975,631,578'Programmable array interconnect network'19975,552,721'Method and system for enhanced drive in programmmable gate arrays'19965,341,310'Wiring layout design method and system for integrated circuits'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2011Patents assigned to IBM (49)· patent assignee history
1994–2001Based in Burlington, VT, US· patent location history
1997–1998Patents assigned to ATMEL CORP (3)· patent assignee history
1997Patents assigned to CADENCE DESIGN SYSTEMS INC (1)· patent assignee history
1997–2011Based in South Burlington, VT, US· patent location history
1998Based in Chittenden County, VT, US· patent location history
2005Patents assigned to LSI LOGIC CORP (1)· patent assignee history
2005Based in Boring, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 49 | 1994–2011 |
| ATMEL CORP | 3 | 1997–1998 |
| CADENCE DESIGN SYSTEMS INC | 1 | 1997 |
| LSI LOGIC CORP | 1 | 2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 34 | 1997–2011 |
| Burlington, VT, US | 14 | 1994–2001 |
| Boring, OR, US | 1 | 2005 |
| Chittenden County, VT, US | 1 | 1998 |